hlslibs / ac_ml
Algorithmic C Machine Learning Library
☆22Updated 3 months ago
Alternatives and similar repositories for ac_ml:
Users that are interested in ac_ml are comparing it to the libraries listed below
- ☆26Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- ☆3Updated 3 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 5 years ago
- Ratatoskr NoC Simulator☆24Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆64Updated 2 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆37Updated 6 months ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆24Updated 2 weeks ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆38Updated 7 months ago
- cycle accurate Network-on-Chip Simulator☆27Updated last year
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- ☆26Updated 4 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 5 years ago
- Tutorials on HLS Design☆51Updated 5 years ago
- Reconfigurable Binary Engine☆16Updated 4 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- ☆43Updated 6 years ago
- Xilinx AXI VIP example of use☆36Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago
- CNN accelerator☆28Updated 7 years ago
- ☆59Updated last year