hlslibs / ac_mlLinks
Algorithmic C Machine Learning Library
☆26Updated 9 months ago
Alternatives and similar repositories for ac_ml
Users that are interested in ac_ml are comparing it to the libraries listed below
Sorting:
- Tutorials on HLS Design☆52Updated 5 years ago
- HLS for Networks-on-Chip☆36Updated 4 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆89Updated last week
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆58Updated last year
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 2 weeks ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆27Updated 5 years ago
- Development of a Network on Chip Simulation using SystemC.☆34Updated 8 years ago
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 4 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆40Updated this week
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated last week
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 7 months ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆81Updated 2 years ago
- Train and deploy LUT-based neural networks on FPGAs☆98Updated last year
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆125Updated 2 years ago
- A repository for SystemC Learning examples☆71Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆52Updated 8 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- BlackParrot on Zynq☆47Updated 7 months ago
- ☆76Updated last week
- matrix-coprocessor for RISC-V☆19Updated 5 months ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆91Updated 9 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 7 months ago
- ☆49Updated 5 months ago
- ☆60Updated 5 years ago