Xtra-Computing / ReGraphLinks
Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines
☆22Updated 3 years ago
Alternatives and similar repositories for ReGraph
Users that are interested in ReGraph are comparing it to the libraries listed below
Sorting:
- [HPCA 2022] GCoD: Graph Convolutional Network Acceleration via Dedicated Algorithm and Accelerator Co-Design☆38Updated 3 years ago
- An end-to-end GCN inference accelerator written in HLS☆18Updated 3 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆44Updated 2 years ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆74Updated 3 years ago
- NeuraChip Accelerator Simulator☆15Updated last year
- Serpens is an HBM FPGA accelerator for SpMV☆22Updated last year
- ☆29Updated 4 years ago
- STONNE Simulator integrated into SST Simulator☆22Updated last year
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 4 years ago
- ☆20Updated last year
- ☆50Updated 6 months ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆13Updated 3 years ago
- ☆16Updated 2 years ago
- MICRO22 artifact evaluation for Sparseloop☆45Updated 3 years ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆68Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- ☆10Updated 2 years ago
- ☆11Updated 4 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆78Updated 7 months ago
- PIMeval simulator and PIMbench suite☆39Updated 3 weeks ago
- PUMA Compiler☆30Updated 2 months ago
- This repo is to collect the state-of-the-art GNN hardware acceleration paper☆54Updated 4 years ago
- [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs☆18Updated last year
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- including compiler to encode DGL GNN model to instructions, runtime software to transfer data and control the accelerator, and hardware v…☆13Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- ☆19Updated 3 years ago