Open source GPU extension for RISC-V
☆71Apr 6, 2021Updated 4 years ago
Alternatives and similar repositories for rv64x-base
Users that are interested in rv64x-base are comparing it to the libraries listed below
Sorting:
- RV32I Open Source GPU☆14Feb 9, 2021Updated 5 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆119May 11, 2023Updated 2 years ago
- Vortex Graphics☆92Oct 2, 2024Updated last year
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Feb 6, 2024Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- SPIR-V fragment shader GPU core based on RISC-V☆44May 26, 2021Updated 4 years ago
- RISC-V Nox core☆71Jul 22, 2025Updated 7 months ago
- ☆21Updated this week
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆875Updated this week
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 3 years ago
- ☆1,913Updated this week
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆37Updated this week
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆14Jul 22, 2020Updated 5 years ago
- tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog☆64Jul 14, 2021Updated 4 years ago
- The simple pingora reverse proxy code sample.☆10Jun 19, 2024Updated last year
- RV64GC Linux Capable RISC-V Core☆54Oct 20, 2025Updated 4 months ago
- OpenSource GPU, in Verilog, loosely based on RISC-V ISA☆1,273Nov 22, 2024Updated last year
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆18Feb 12, 2024Updated 2 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Apr 11, 2023Updated 2 years ago
- Zig wrapper around the RISC-V SBI specification☆19Mar 2, 2026Updated last week
- A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.☆14Nov 23, 2022Updated 3 years ago
- Experimental breakout board for a signle 200-ball WFBGA LPDDR4 chip in SO-DIMM DDR4 form factor.☆18Dec 11, 2025Updated 2 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Dec 24, 2024Updated last year
- RISC-V System on Chip Template☆161Aug 18, 2025Updated 6 months ago
- Reconfigurable Binary Engine☆17Mar 23, 2021Updated 4 years ago
- A Flyweight MBIST Block - FPGA synthesizable, Multi-algorithm integrated☆19Jan 27, 2019Updated 7 years ago
- Kendryte K210 BSP for RT-Thread☆16Dec 23, 2018Updated 7 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆77Dec 30, 2019Updated 6 years ago
- Token ring communication protocol for low-cost, low-power embedded devices communicating over UART☆17May 3, 2018Updated 7 years ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆39Jan 15, 2024Updated 2 years ago
- Graphics SIG organizational information☆40Jan 10, 2024Updated 2 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆142Feb 24, 2025Updated last year
- Gem5 with PCI Express integrated.☆23Sep 29, 2018Updated 7 years ago
- A Fast, Low-Overhead On-chip Network☆271Updated this week
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆50Jan 2, 2025Updated last year
- Vibe Coding A GPGPU via Cursor + Gemini3 Pro☆55Nov 23, 2025Updated 3 months ago
- ☆18Dec 15, 2022Updated 3 years ago
- ☆21May 14, 2025Updated 9 months ago
- 3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.☆92Oct 3, 2020Updated 5 years ago