zxmarcos / huedeon-gpuLinks
FPGA GPU design for DE1-SoC
☆72Updated 3 years ago
Alternatives and similar repositories for huedeon-gpu
Users that are interested in huedeon-gpu are comparing it to the libraries listed below
Sorting:
- 3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.☆85Updated 4 years ago
- Minimal DVI / HDMI Framebuffer☆83Updated 4 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 4 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆91Updated 5 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- A basic GPU for altera FPGAs☆76Updated 5 years ago
- A pipelined RISC-V processor☆57Updated last year
- ☆59Updated 3 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆79Updated last year
- Doom classic port to lightweight RISC‑V☆94Updated 2 years ago
- Wishbone interconnect utilities☆41Updated 5 months ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆30Updated 4 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆47Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆93Updated last week
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆55Updated last year
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- Another tiny RISC-V implementation☆56Updated 3 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆89Updated 6 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆42Updated 4 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆115Updated last year
- Naive Educational RISC V processor☆84Updated last month
- Xilinx Unisim Library in Verilog☆79Updated 4 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆95Updated last month
- ☆134Updated 7 months ago
- A Video display simulator☆171Updated 2 months ago
- Graphics demos☆110Updated last year
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- Dual-issue RV64IM processor for fun & learning☆62Updated 2 years ago
- RISC-V Nox core☆66Updated 3 months ago
- ☆70Updated 10 months ago