zxmarcos / huedeon-gpu
FPGA GPU design for DE1-SoC
☆70Updated 2 years ago
Related projects: ⓘ
- 3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.☆67Updated 3 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆63Updated 2 years ago
- A basic GPU for altera FPGAs☆63Updated 5 years ago
- Minimal DVI / HDMI Framebuffer☆74Updated 4 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆84Updated 4 years ago
- SPIR-V fragment shader GPU core based on RISC-V☆36Updated 3 years ago
- A pipelined RISC-V processor☆47Updated 9 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆39Updated 10 months ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆78Updated 4 years ago
- Naive Educational RISC V processor☆69Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆57Updated 5 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆54Updated this week
- Wishbone interconnect utilities☆34Updated 3 months ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆58Updated last year
- FPGA based microcomputer sandbox for software and RTL experimentation☆41Updated this week
- ☆56Updated 3 years ago
- Tools for FPGA development.☆43Updated last year
- Reusable Verilog 2005 components for FPGA designs☆34Updated last year
- A Video display simulator☆154Updated last month
- Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer☆25Updated 2 years ago
- Another tiny RISC-V implementation☆51Updated 3 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆69Updated 5 months ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆28Updated 3 years ago
- Dual-issue RV64IM processor for fun & learning☆56Updated last year
- ☆35Updated 2 years ago
- ☆117Updated last year
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆113Updated 3 years ago
- ☆31Updated last year
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆86Updated 3 years ago
- Experiments with fixed function renderers and Chisel HDL☆56Updated 5 years ago