kagandikmen / TPU.svLinks
Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1
☆18Updated last month
Alternatives and similar repositories for TPU.sv
Users that are interested in TPU.sv are comparing it to the libraries listed below
Sorting:
- CMake based hardware build system☆30Updated 2 weeks ago
- ☆19Updated last year
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 9 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 5 months ago
- RISC-V Nox core☆66Updated 2 weeks ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- A tool for synthesizing Verilog programs☆95Updated this week
- pulp_soc is the core building component of PULP based SoCs☆80Updated 5 months ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆19Updated 2 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆63Updated 6 months ago
- Simple UVM environment for experimenting with Verilator.☆23Updated 3 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Benchmarks for High-Level Synthesis☆10Updated 2 years ago
- ☆73Updated this week
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 2 months ago
- ☆59Updated 3 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- ☆33Updated 2 years ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated this week
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆64Updated 9 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆36Updated 2 years ago