Alternatives and similar repositories for autoGenILA:

Users that are interested in autoGenILA are comparing it to the libraries listed below

• fangwenji / tacas23-wasim
  ☆12Updated 2 years ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆9Updated 5 months ago
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 5 years ago
• amahzoon / RevSCA-2.0
  ☆10Updated 5 years ago
• CoriolisSP / FuzzBtor2
  Random Generator of Btor2 Files
  ☆10Updated last year
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆28Updated 8 months ago
• yaoxufeng / RTLRewriter-Bench
  ☆29Updated 10 months ago
• ycunxi / ACEC_benchmarks
  Arithmetic multiplier benchmarks
  ☆11Updated 7 years ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆16Updated 3 months ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆50Updated 3 months ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆26Updated 7 months ago
• GATECH-EIC / LLM4HWDesign_Starting_Toolkit
  LLM4HWDesign Starting Toolkit
  ☆17Updated 6 months ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆11Updated 3 years ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆26Updated 5 months ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆16Updated last year
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆13Updated last week
• iscas-tis / CHA
  ☆18Updated 9 months ago
• Entropy-xcy / sns
  ☆15Updated 2 years ago
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated last year
• yzwangfeng / reram-synthesis
  A synthesis flow for hybrid processing-in-RRAM modes
  ☆12Updated 3 years ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆20Updated 2 months ago
• amahzoon / genmul
  ☆16Updated 4 years ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆22Updated 4 years ago
• iwls2020-lsml-contest / iwls2020-lsml-contest
  ☆21Updated 2 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated 11 months ago
• cornell-zhang / datuner
  DATuner Repository
  ☆18Updated 6 years ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆32Updated 2 months ago
• hkust-zhiyao / RTL-Timer
  Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
  ☆23Updated 9 months ago
• icgrp / hipr
  ☆15Updated 2 years ago