yuzeng2333 / autoGenILA
Automatic generation of architecture-level models for hardware from its RTL design.
☆14Updated last year
Alternatives and similar repositories for autoGenILA:
Users that are interested in autoGenILA are comparing it to the libraries listed below
- ☆12Updated 2 years ago
- ☆13Updated 4 years ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12Updated 5 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆27Updated 7 months ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆14Updated 8 years ago
- This is a python repo for flattening Verilog☆15Updated last month
- ☆15Updated 4 years ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆26Updated 5 months ago
- ☆11Updated 4 years ago
- Random Generator of Btor2 Files☆9Updated last year
- DATuner Repository☆18Updated 6 years ago
- This is a repo to store circuit design datasets☆15Updated last year
- ☆21Updated 2 years ago
- ☆14Updated 2 years ago
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆15Updated 8 months ago
- Hardware Model Checker☆30Updated this week
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 3 years ago
- ☆12Updated 3 years ago
- A Generic Distributed Auto-Tuning Infrastructure☆21Updated 3 years ago
- ILA Model Database☆22Updated 4 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆49Updated last month
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆17Updated 4 months ago
- ☆25Updated 9 months ago
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆13Updated 2 years ago
- LLM4HWDesign Starting Toolkit☆17Updated 4 months ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 3 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆23Updated 3 months ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆19Updated 3 months ago