Alternatives and similar repositories for autoGenILA

Users that are interested in autoGenILA are comparing it to the libraries listed below

• fangwenji / tacas23-wasim
  ☆12Updated 2 years ago
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆21Updated 2 months ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 6 years ago
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆13Updated last month
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆10Updated 7 months ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆32Updated 10 months ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆16Updated 3 weeks ago
• amahzoon / RevSCA-2.0
  ☆10Updated 5 years ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆26Updated 9 months ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 4 months ago
• CoriolisSP / FuzzBtor2
  Random Generator of Btor2 Files
  ☆10Updated last year
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆19Updated last week
• ycunxi / ACEC_benchmarks
  Arithmetic multiplier benchmarks
  ☆11Updated 7 years ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆17Updated last year
• amahzoon / genmul
  ☆16Updated 4 years ago
• sterin / super-prove-build
  ☆13Updated 4 years ago
• iscas-tis / CHA
  ☆19Updated 10 months ago
• UCSBarchlab / owl
  Control Logic Synthesis: Drawing the Rest of the OWL
  ☆11Updated 11 months ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆11Updated 3 years ago
• efeslab / hardware-bugbase
  ☆18Updated 11 months ago
• yaoxufeng / RTLRewriter-Bench
  ☆31Updated last year
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆25Updated last year
• gpt4rtl / AutoSVA2
  ☆15Updated last year
• morenes / AutoCC
  Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…
  ☆17Updated 7 months ago
• iwls2020-lsml-contest / iwls2020-lsml-contest
  ☆21Updated 2 years ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆22Updated 4 years ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆30Updated 7 months ago
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 3 years ago
• laiyao1 / ArithTreeRL
  The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"
  ☆13Updated 8 months ago