Alternatives and similar repositories for Dataset

Users that are interested in Dataset are comparing it to the libraries listed below

• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆77Updated last year
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆137Updated 2 years ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆29Updated 3 years ago
• geziangfinn / easyPlace
  Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS
  ☆50Updated 10 months ago
• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆138Updated 2 months ago
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆129Updated last year
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆42Updated last year
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆56Updated 8 months ago
• ASU-VDA-Lab / 2024_ICCAD_Contest_Gate_Sizing_Benchmark
  ☆23Updated 10 months ago
• cuhk-eda / dr-cu
  Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
  ☆137Updated 2 years ago
• ASU-VDA-Lab / ASP-DAC24-Tutorial
  This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024
  ☆52Updated 8 months ago
• cuhk-eda / cu-gr-2
  ☆46Updated last year
• The-OpenROAD-Project / RePlAce
  RePlAce global placement tool
  ☆239Updated 5 years ago
• NYU-MLDA / OpenABC
  OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…
  ☆130Updated last month
• ABKGroup / TritonRoute-WXL
  ☆33Updated 4 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆90Updated last month
• ABKGroup / PlacementEssentialReadings
  ☆57Updated 4 years ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆75Updated 7 years ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆31Updated last year
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆61Updated last week
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• zshi0616 / DeepGate2
  ☆29Updated last year
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆105Updated last year
• asyncvlsi / lefdef
  Mirror of the Si2 LEF/DEF parser (v5.8)
  ☆17Updated 3 years ago
• TILOS-AI-Institute / MacroPlacement
  Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source
  ☆281Updated 4 months ago
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆177Updated 3 months ago
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆210Updated 2 months ago
• TILOS-AI-Institute / HypergraphPartitioning
  Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes
  ☆71Updated 3 months ago
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆51Updated 3 months ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆31Updated 3 years ago