☆18Jul 11, 2021Updated 4 years ago
Alternatives and similar repositories for HyperFuzzer
Users that are interested in HyperFuzzer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆15Mar 23, 2026Updated 2 months ago
- Fuzz everything! Now let's fuzz chip!☆41Apr 17, 2026Updated last month
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- ☆16May 2, 2026Updated last month
- ☆18Nov 19, 2023Updated 2 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- ☆15Feb 6, 2021Updated 5 years ago
- ☆23Mar 12, 2026Updated 2 months ago
- Automated Repair of Verilog Hardware Descriptions☆39Jan 16, 2025Updated last year
- This repository includes the data and scripts utilized in the study titled "Improving LLM-based Verilog Code Generation with Data Augment…☆14Mar 24, 2025Updated last year
- A Modular Open-Source Hardware Fuzzing Framework☆37Dec 14, 2021Updated 4 years ago
- GPU-enabled Hardware Fuzzer using Genetic Algorithm☆20Jul 12, 2023Updated 2 years ago
- ☆18Jul 12, 2024Updated last year
- Fix syntax errors of LLM-generated RTL☆51May 23, 2024Updated 2 years ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆63Mar 26, 2026Updated 2 months ago
- This is a repo to store circuit design datasets☆18Jan 17, 2024Updated 2 years ago
- The code of AAAI20 paper "Efficient Inference of Optimal Decision Trees"☆10Jun 26, 2020Updated 5 years ago
- ☆31Mar 31, 2025Updated last year
- ☆26Mar 1, 2023Updated 3 years ago
- Fuzzing for SpinalHDL☆17Oct 10, 2022Updated 3 years ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆11May 24, 2019Updated 7 years ago
- NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)☆25May 20, 2026Updated 3 weeks ago
- All the tools you need to reproduce the CellIFT paper experiments☆24Feb 11, 2025Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆90Jan 20, 2023Updated 3 years ago
- ☆102May 27, 2024Updated 2 years ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆14May 7, 2022Updated 4 years ago
- ☆13Jan 20, 2023Updated 3 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆63Oct 28, 2024Updated last year
- Reasoning LLMs optimized for Chisel code generation☆27Jun 19, 2025Updated 11 months ago
- Iodine: Verifying Constant-Time Execution of Hardware☆18Mar 29, 2021Updated 5 years ago
- Lock-free elimination back-off stack☆13Jan 6, 2022Updated 4 years ago
- A fork of Yosys that integrates the CellIFT pass☆13Apr 21, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Showcase examples for EPFL logic synthesis libraries☆206Apr 5, 2024Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆102Mar 29, 2024Updated 2 years ago
- ☆21Jun 12, 2024Updated last year
- ☆25Nov 15, 2021Updated 4 years ago
- ☆11Aug 10, 2021Updated 4 years ago
- ☆32Nov 2, 2025Updated 7 months ago
- ☆10Oct 15, 2021Updated 4 years ago