☆18Jul 11, 2021Updated 4 years ago
Alternatives and similar repositories for HyperFuzzer
Users that are interested in HyperFuzzer are comparing it to the libraries listed below
Sorting:
- Fuzz everything! Now let's fuzz chip!☆35Feb 11, 2026Updated last month
- ☆15Sep 3, 2024Updated last year
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- ☆17Nov 19, 2023Updated 2 years ago
- ☆13Feb 6, 2021Updated 5 years ago
- ☆20Mar 12, 2026Updated last week
- Automated Repair of Verilog Hardware Descriptions☆37Jan 16, 2025Updated last year
- This repository includes the data and scripts utilized in the study titled "Improving LLM-based Verilog Code Generation with Data Augment…☆14Mar 24, 2025Updated 11 months ago
- A Modular Open-Source Hardware Fuzzing Framework☆37Dec 14, 2021Updated 4 years ago
- GPU-enabled Hardware Fuzzer using Genetic Algorithm☆20Jul 12, 2023Updated 2 years ago
- Fix syntax errors of LLM-generated RTL☆44May 23, 2024Updated last year
- ☆19Jul 12, 2024Updated last year
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- ☆63Dec 27, 2025Updated 2 months ago
- ☆28Mar 31, 2025Updated 11 months ago
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- The code of AAAI20 paper "Efficient Inference of Optimal Decision Trees"☆10Jun 26, 2020Updated 5 years ago
- Fuzzing for SpinalHDL☆17Oct 10, 2022Updated 3 years ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12May 24, 2019Updated 6 years ago
- NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)☆24Dec 21, 2025Updated 3 months ago
- All the tools you need to reproduce the CellIFT paper experiments☆24Feb 11, 2025Updated last year
- ☆89Jan 20, 2023Updated 3 years ago
- ☆102May 27, 2024Updated last year
- ☆99Dec 1, 2023Updated 2 years ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆14May 7, 2022Updated 3 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆53Oct 28, 2024Updated last year
- ☆13Jan 20, 2023Updated 3 years ago
- ☆12Oct 6, 2025Updated 5 months ago
- Iodine: Verifying Constant-Time Execution of Hardware☆15Mar 29, 2021Updated 4 years ago
- Lock-free elimination back-off stack☆12Jan 6, 2022Updated 4 years ago
- A fork of Yosys that integrates the CellIFT pass☆13Jul 23, 2025Updated 7 months ago
- Showcase examples for EPFL logic synthesis libraries☆203Apr 5, 2024Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆99Mar 29, 2024Updated last year
- ☆20Jun 12, 2024Updated last year
- ILA Model Database☆24Sep 27, 2020Updated 5 years ago
- ☆26Nov 15, 2021Updated 4 years ago
- ☆11Aug 10, 2021Updated 4 years ago
- ☆25Nov 2, 2025Updated 4 months ago
- ☆10Oct 15, 2021Updated 4 years ago