Alternatives and similar repositories for AutoBench:

Users that are interested in AutoBench are comparing it to the libraries listed below

• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆26Updated 5 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆44Updated 6 months ago
• Entropy-xcy / sns
  ☆15Updated 2 years ago
• zshi0616 / python-deepgate
  ☆22Updated 9 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆51Updated 4 months ago
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆18Updated last year
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆16Updated 2 months ago
• yaoxufeng / RTLRewriter-Bench
  ☆28Updated 10 months ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆44Updated 2 months ago
• wjrforcyber / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆32Updated 3 weeks ago
• NVlabs / Differentiable-Global-Router
  ☆17Updated 4 months ago
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆97Updated 4 months ago
• amahzoon / genmul
  ☆16Updated 4 years ago
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆12Updated 9 months ago
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆17Updated 6 months ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆49Updated 2 months ago
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated 11 months ago
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆13Updated 2 years ago
• gpt4rtl / AutoSVA2
  ☆13Updated last year
• hkust-zhiyao / RTL-Timer
  Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
  ☆22Updated 8 months ago
• fangwenji / tacas23-wasim
  ☆12Updated 2 years ago
• pku-dasys / easymac
  ☆16Updated 3 years ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆15Updated last year
• zshi0616 / DeepGate2
  ☆28Updated last year
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆9Updated 5 months ago
• cure-lab / DeepGate2
  ☆14Updated last year
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆51Updated 5 months ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆28Updated 8 months ago
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆19Updated 3 months ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆26Updated 7 months ago