AutoBench / AutoBench
☆17Updated last week
Related projects ⓘ
Alternatives and complementary repositories for AutoBench
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆17Updated 4 months ago
- ☆21Updated 4 months ago
- Research paper based on or related to ABC.☆15Updated last week
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆20Updated 3 weeks ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆35Updated 2 months ago
- An open-source benchmark for generating design RTL with natural language☆70Updated 2 weeks ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆47Updated 2 weeks ago
- ☆12Updated 2 years ago
- This is a python repo for flattening Verilog☆13Updated last month
- ☆27Updated 11 months ago
- ☆50Updated 3 weeks ago
- A circuit-element level explainer to explain machine learning model's prediction on chip layouts.☆17Updated last year
- Logic optimization and technology mapping tool.☆17Updated last year
- GPU-based logic synthesis tool☆68Updated 4 months ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆15Updated last month
- This is a repo to store circuit design datasets☆15Updated 10 months ago
- ☆20Updated 6 months ago
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆13Updated last month
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆11Updated 2 years ago
- ☆19Updated 2 weeks ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆36Updated last month
- ☆15Updated 2 years ago
- ☆37Updated 4 months ago
- Collection of digital hardware modules & projects (benchmarks)☆33Updated last week
- Verilog evaluation benchmark for large language model☆179Updated 3 months ago
- ☆14Updated last year
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆75Updated 3 weeks ago
- MLCAD 2020: Reinforcement for logic optimization sequence exploration☆26Updated 4 years ago
- Simple Python interface for ABC☆23Updated last year
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆115Updated last month