AutoBench / AutoBenchLinks
☆24Updated 2 months ago
Alternatives and similar repositories for AutoBench
Users that are interested in AutoBench are comparing it to the libraries listed below
Sorting:
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆31Updated 7 months ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆17Updated 2 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆50Updated 3 weeks ago
- An open-source benchmark for generating design RTL with natural language☆112Updated 7 months ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆15Updated 2 years ago
- ☆22Updated last year
- ☆18Updated 2 years ago
- ☆22Updated 2 months ago
- ☆52Updated 3 weeks ago
- This is a python repo for flattening Verilog☆18Updated last month
- Collection of digital hardware modules & projects (benchmarks)☆59Updated last month
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆50Updated 5 months ago
- ☆31Updated 11 months ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆22Updated 2 months ago
- ☆14Updated 9 months ago
- This is a repo to store circuit design datasets☆18Updated last year
- ☆31Updated last year
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆13Updated 8 months ago
- ☆25Updated last year
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDA☆25Updated last month
- ☆46Updated 8 months ago
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆17Updated 6 months ago
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆42Updated 6 months ago
- Benchmarks for Approximate Circuit Synthesis☆16Updated 4 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆49Updated 5 months ago
- LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust☆27Updated last year
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated last year
- ☆155Updated 8 months ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆203Updated 4 months ago
- ☆23Updated 7 months ago