Alternatives and similar repositories for cascade-meta

Users that are interested in cascade-meta are comparing it to the libraries listed below

• comsec-group / cellift-meta
  All the tools you need to reproduce the CellIFT paper experiments
  ☆21Updated 7 months ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 4 years ago
• hackdac / hackdac_2018_beta
  The SoC used for the beta phase of Hack@DAC 2018.
  ☆17Updated 5 years ago
• OpenXiangShan / xfuzz
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers
  ☆21Updated last week
• compsec-snu / specdoctor
  ☆25Updated 2 years ago
• comsec-group / encarsia
  ☆21Updated 5 months ago
• dian-lun-lin / GenFuzz
  GPU-enabled Hardware Fuzzer using Genetic Algorithm
  ☆18Updated 2 years ago
• hkustgz-zhang-lab / HW-Formal-Paper
  Recent papers related to hardware formal verification.
  ☆73Updated last year
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆17Updated 4 years ago
• ekiwi / simulator-independent-coverage
  Project Repo for the Simulator Independent Coverage Research
  ☆20Updated 2 years ago
• skmuduli92 / HyperFuzzer
  ☆16Updated 4 years ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆34Updated 3 years ago
• googleinterns / hw-fuzzing
  ☆87Updated 2 years ago
• ekiwi / rfuzz
  rfuzz: coverage-directed fuzzing for RTL research platform
  ☆110Updated 3 years ago
• iscas-tis / ChiRVFormal
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆14Updated 3 months ago
• compsec-snu / difuzz-rtl
  ☆93Updated last year
• bu-icsg / ProcessorFuzz
  ☆13Updated last year
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆64Updated last week
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated 6 months ago
• ics-jku / spinalfuzz
  Fuzzing for SpinalHDL
  ☆16Updated 2 years ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆81Updated this week
• sycuricon / MorFuzz
  Artifact evaluation of paper: MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation
  ☆42Updated 4 months ago
• iscas-tis / CHA
  ☆19Updated last year
• riscv-boom / boom-attacks
  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
  ☆65Updated 5 years ago
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 6 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆26Updated 2 months ago
• efeslab / asplos22-hardware-debugging-artifact
  ☆13Updated last year
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆29Updated 5 months ago
• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆16Updated 4 years ago
• yaohsiaopid / rtl2uspec
  ☆11Updated 2 months ago