Generative Benchmark for LLM-Aided Hardware Design
☆30Jun 4, 2025Updated last year
Alternatives and similar repositories for GenBen
Users that are interested in GenBen are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A SystemVerilog Assertion dataset to improve hardware verification with LLMs.☆28Jun 9, 2025Updated last year
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆67Oct 28, 2024Updated last year
- RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24☆34Jun 5, 2024Updated 2 years ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆44Apr 3, 2025Updated last year
- ☆30Jan 30, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Contract-Aware RTL Code Generation Agents with Temporal Tracing, Slicing and Formal Verification☆23Jan 28, 2026Updated 6 months ago
- ☆16May 2, 2026Updated 3 months ago
- ☆42Dec 21, 2025Updated 7 months ago
- ☆57Jul 13, 2026Updated 3 weeks ago
- Benchmarking LLM agents on real-world hardware bug repair tasks☆38Aug 1, 2026Updated last week
- ☆30Jun 25, 2024Updated 2 years ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆43Apr 13, 2025Updated last year
- ☆293Jul 8, 2024Updated 2 years ago
- Automated Repair of Verilog Hardware Descriptions☆39Jan 16, 2025Updated last year
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Fast Symbolic Repair of Hardware Design Code☆39Jan 20, 2025Updated last year
- commit rtl and build cosim env☆36Mar 29, 2024Updated 2 years ago
- 软件工程与形式化方法相关前沿工作阅读与分享☆36Oct 27, 2025Updated 9 months ago
- Papers on LLM4EDA from 2023 and 2024☆47Jul 6, 2024Updated 2 years ago
- [DATE 2025] haven: hallucination-mitigated llm for verilog code generation aligned with hdl engineers☆43Jul 9, 2025Updated last year
- ☆18Nov 19, 2023Updated 2 years ago
- A curated list of research and repositories on the novel technique of hardware fuzzing☆27Jun 4, 2026Updated 2 months ago
- ☆49May 18, 2024Updated 2 years ago
- 简洁的测试平台日志,波形(FSDB/VCD),根因分析MCP Server. A Simple and Universal MCP Server to Debug Testbench Simulation Failures Via Log Parsing And Wave…☆61Jul 30, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Fuzz everything! Now let's fuzz chip!☆44Jun 5, 2026Updated 2 months ago
- Fix syntax errors of LLM-generated RTL☆57May 23, 2024Updated 2 years ago
- Reasoning LLMs optimized for Chisel code generation☆26Jun 19, 2025Updated last year
- ☆47Jul 31, 2026Updated last week
- LLM-aided Hardware Design and Verification☆37May 11, 2026Updated 2 months ago
- work in progress, playing around with btor2 in rust☆15Jul 24, 2026Updated 2 weeks ago
- Misc documentation and specifications☆14Feb 26, 2022Updated 4 years ago
- This repository contains 4000 vulnerable hardware designs. Currently this is in Jsonl format for directly using it for fine-tuning LLMs. …☆24Mar 25, 2025Updated last year
- Verilog-Based-NoC-Simulator☆12May 4, 2016Updated 10 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- LLM4HWDesign Starting Toolkit☆20Oct 4, 2024Updated last year
- OpenROAD Agent. This repository contain the model to train and testing the model using EDA Corpus dataset.☆32Jul 24, 2025Updated last year
- This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generati…☆29Sep 25, 2025Updated 10 months ago
- MCP server to read waveform files☆45Aug 1, 2026Updated last week
- Verilog evaluation benchmark for large language model☆458Jul 14, 2025Updated last year
- UVM Book Examples - A Practical Guide to Adopting the Universal Verification Methodology (UVM) Second Edition☆32Jan 20, 2014Updated 12 years ago
- ☆177Mar 10, 2025Updated last year