Alternatives and similar repositories for GenBen

Users that are interested in GenBen are comparing it to the libraries listed below

• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆106Updated 2 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆177Updated last month
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆135Updated 11 months ago
• kuladeepsaireddy / OpenNoc
  ☆37Updated 6 years ago
• ehao222 / ASIC-design-example-RISC-CPU
  Base on Synopsys platform using VCS,DC,ICC,PT.
  ☆12Updated 4 years ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆64Updated 4 years ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆132Updated 7 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆64Updated 3 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆77Updated 7 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆82Updated 7 years ago
• AutoBench / CorrectBench
  ☆25Updated 6 months ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆50Updated 9 months ago
• Ghonimo / Formal-Verification-of-an-AHB2APB-Bridge
  Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…
  ☆20Updated last year
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆39Updated last year
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆59Updated this week
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆69Updated last year
• pulp-platform / fpu
  ☆56Updated 6 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆144Updated last year
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆129Updated 5 years ago
• openhwgroup / cv-hpdcache-verif
  Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
  ☆18Updated 8 months ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆192Updated 3 years ago
• The-OpenROAD-Project / asap7
  ☆201Updated 7 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆215Updated 2 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆89Updated last year
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆78Updated 11 years ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆58Updated 5 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆231Updated this week
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆118Updated 8 months ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆36Updated 4 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆156Updated 11 months ago