Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operates at RTL to exhaustively examine any machine state left by a process after a context switch that creates an execution difference.
☆24Oct 25, 2024Updated last year
Alternatives and similar repositories for AutoCC
Users that are interested in AutoCC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeli…☆24Feb 22, 2024Updated 2 years ago
- ☆18Nov 19, 2023Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆104Mar 29, 2024Updated 2 years ago
- A tool for checking the contract satisfaction for hardware designs☆12Jul 21, 2026Updated last month
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆78Jun 30, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- All the tools you need to reproduce the CellIFT paper experiments☆23Feb 11, 2025Updated last year
- ILAng documentation☆12Nov 2, 2025Updated 10 months ago
- ☆10Nov 19, 2015Updated 10 years ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 3 years ago
- ☆21Jun 12, 2024Updated 2 years ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆17Jun 7, 2021Updated 5 years ago
- Hardware Division Units☆10Jul 17, 2014Updated 12 years ago
- ☆20Dec 29, 2014Updated 11 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Research project from UCI's AICPS lab: using GNNs to enable hardware security and prevent hardware trojans☆10Mar 31, 2021Updated 5 years ago
- ☆16Sep 14, 2020Updated 6 years ago
- ☆15Feb 6, 2021Updated 5 years ago
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆20Jul 8, 2026Updated 2 months ago
- Code repository for Coppelia tool☆22Nov 12, 2020Updated 5 years ago
- ☆13Jan 20, 2023Updated 3 years ago
- Modified version of PULP Ara to support Vector Cryptography (Zvk) Instructions☆16Jan 21, 2026Updated 7 months ago
- ☆18Nov 9, 2022Updated 3 years ago
- ☆27Feb 19, 2026Updated 7 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- ☆26Mar 1, 2023Updated 3 years ago
- VerMFi: Verification tool for Masked implementations and Fault injection. Set of tools to evaluate resistance of secure hardware against …☆21Nov 18, 2019Updated 6 years ago
- ☆18Jul 12, 2024Updated 2 years ago
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Jun 4, 2019Updated 7 years ago
- Heterogeneous simulator for DECADES Project☆32May 23, 2024Updated 2 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…☆26Sep 26, 2024Updated last year
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆70Oct 18, 2019Updated 6 years ago
- ☆19Dec 21, 2020Updated 5 years ago
- SAT-based ATPG using TG-Pro model☆20Jun 5, 2018Updated 8 years ago
- ☆23Mar 12, 2026Updated 6 months ago
- A fork of Yosys that integrates the CellIFT pass☆14Sep 12, 2026Updated last week
- UCLID5: formal modeling, verification, and synthesis of computational systems☆157Mar 2, 2026Updated 6 months ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆69Oct 28, 2024Updated last year