Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operates at RTL to exhaustively examine any machine state left by a process after a context switch that creates an execution difference.
☆22Oct 25, 2024Updated last year
Alternatives and similar repositories for AutoCC
Users that are interested in AutoCC are comparing it to the libraries listed below
Sorting:
- MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeli…☆21Feb 22, 2024Updated 2 years ago
- ☆17Nov 19, 2023Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆99Mar 29, 2024Updated last year
- A tool for checking the contract satisfaction for hardware designs☆12Nov 4, 2025Updated 4 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆75Jun 30, 2024Updated last year
- All the tools you need to reproduce the CellIFT paper experiments☆24Feb 11, 2025Updated last year
- ☆20Jun 12, 2024Updated last year
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆17Jun 7, 2021Updated 4 years ago
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- ☆20Dec 29, 2014Updated 11 years ago
- ☆25Feb 19, 2026Updated last month
- ☆14Sep 14, 2020Updated 5 years ago
- ☆13Feb 6, 2021Updated 5 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆51Oct 28, 2024Updated last year
- Modified version of PULP Ara to support Vector Cryptography (Zvk) Instructions☆17Jan 21, 2026Updated last month
- ☆13Jan 20, 2023Updated 3 years ago
- This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…☆21Mar 2, 2023Updated 3 years ago
- Code repository for Coppelia tool☆23Nov 12, 2020Updated 5 years ago
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆20Sep 4, 2025Updated 6 months ago
- ☆15May 24, 2023Updated 2 years ago
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- ☆25Mar 1, 2023Updated 3 years ago
- ☆19Jul 12, 2024Updated last year
- 大三上做的本科毕设,包含BNN的替代梯度训练,verilog电路实现,完成180nm工艺流片。☆22Jun 30, 2025Updated 8 months ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…☆26Sep 26, 2024Updated last year
- Heterogeneous simulator for DECADES Project