fusesoc / fusesoc-generatorsLinks
A collection of core generators to use with FuseSoC
☆16Updated 11 months ago
Alternatives and similar repositories for fusesoc-generators
Users that are interested in fusesoc-generators are comparing it to the libraries listed below
Sorting:
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 8 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Announcements related to Verilator☆39Updated 5 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 6 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆48Updated 3 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- ☆20Updated 3 years ago
- ☆44Updated 5 years ago
- ☆12Updated 5 years ago
- ideas and eda software for vlsi design☆50Updated last week
- SystemVerilog Development Environment☆54Updated 3 years ago
- AMC: Asynchronous Memory Compiler☆50Updated 5 years ago
- FuseSoC standard core library☆146Updated 2 months ago
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆38Updated 11 months ago
- ☆55Updated last year
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 3 years ago
- SVA examples and demonstration☆16Updated 4 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- BAG framework☆41Updated last year
- ☆38Updated 3 years ago
- Mutation Cover with Yosys (MCY)☆85Updated last month
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- Benchmarks for Yosys development☆24Updated 5 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆23Updated 5 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago