fusesoc / fusesoc-generators
A collection of core generators to use with FuseSoC
☆16Updated 8 months ago
Alternatives and similar repositories for fusesoc-generators:
Users that are interested in fusesoc-generators are comparing it to the libraries listed below
- Benchmarks for Yosys development☆24Updated 5 years ago
- Extended and external tests for Verilator testing☆16Updated last week
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- ☆18Updated 4 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- ☆36Updated 2 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆29Updated 9 months ago
- LibreSilicon's Standard Cell Library Generator☆18Updated 11 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Updated last year
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Updated 3 weeks ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 5 years ago
- ☆33Updated 2 years ago
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆48Updated 8 months ago
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆48Updated 2 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆27Updated 3 months ago
- ☆22Updated last year
- RISC-V processor☆29Updated 2 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- A padring generator for ASICs☆25Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 11 months ago
- Cross EDA Abstraction and Automation☆36Updated last week
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆30Updated 3 years ago
- ☆16Updated 5 months ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆17Updated 5 months ago
- The source code that empowers OpenROAD Cloud☆12Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago