Alternatives and similar repositories for fusesoc-generators:

Users that are interested in fusesoc-generators are comparing it to the libraries listed below

• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated last week
• ZipCPU / videozip
  A ZipCPU SoC for the Nexys Video board supporting video functionality
  ☆17Updated 4 months ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• dawsonjon / chips_v
  RISC-V System on Chip Builder
  ☆11Updated 4 years ago
• vsdip / vsdflow
  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…
  ☆15Updated 4 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆23Updated 5 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆22Updated last week
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• SymbioticEDA / getting-started-FV
  ☆18Updated 4 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 8 months ago
• m-kru / fsva
  FuseSoc Verification Automation
  ☆22Updated 2 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆18Updated 10 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆39Updated last year
• bobbl / rudolv
  RISC-V processor
  ☆29Updated 2 years ago
• merldsu / SAP_FPU
  This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.
  ☆18Updated 2 years ago
• klessydra / T13x
  An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …
  ☆47Updated 7 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• dpretet / svlogger
  SystemVerilog Logger
  ☆17Updated 2 years ago
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆27Updated last year
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• efabless / raptor
  Arm Cortex-M0 based Customizable SoC for IoT Applications
  ☆12Updated 4 years ago
• SystemRDL / PeakRDL-cheader
  ☆12Updated 2 months ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆32Updated 10 months ago
• efabless / caravel-lite
  ☆15Updated 4 months ago
• SymbioticEDA / sva-demos
  SVA examples and demonstration
  ☆16Updated 4 years ago
• openhwgroup / cve2
  The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…
  ☆38Updated last week
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 3 years ago