fusesoc / fusesoc-generatorsLinks
A collection of core generators to use with FuseSoC
☆16Updated last year
Alternatives and similar repositories for fusesoc-generators
Users that are interested in fusesoc-generators are comparing it to the libraries listed below
Sorting:
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 11 months ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 10 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 3 weeks ago
- ☆50Updated 8 months ago
- ☆44Updated 5 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- ☆56Updated 2 years ago
- Announcements related to Verilator☆41Updated 5 years ago
- ideas and eda software for vlsi design☆50Updated this week
- ☆38Updated 3 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆49Updated 3 years ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 4 years ago
- SVA examples and demonstration☆16Updated 5 years ago
- FPGA tool performance profiling☆102Updated last year
- submission repository for efabless mpw6 shuttle☆30Updated last year
- An open source PDK using TIGFET 10nm devices.☆51Updated 2 years ago
- ☆43Updated 8 months ago
- Collection of test cases for Yosys☆17Updated 3 years ago
- Python Tool for UVM Testbench Generation☆54Updated last year
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 9 months ago
- LibreSilicon's Standard Cell Library Generator☆20Updated this week
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆32Updated 4 years ago
- ☆67Updated 2 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 5 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago