Alternatives and similar repositories for amaranth-soc:

Users that are interested in amaranth-soc are comparing it to the libraries listed below

• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 3 years ago
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆108Updated 3 weeks ago
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆28Updated 4 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆78Updated 4 months ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 2 years ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆56Updated this week
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆89Updated 5 months ago
• sparrowgrine / prjtritium
  ☆22Updated 2 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆36Updated 3 years ago
• bieganski / mtkcpu
  RISC-V CPU implementation in Amaranth HDL (aka nMigen)
  ☆28Updated 6 months ago
• openXC7 / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆41Updated this week
• pieter3d / simview
  ☆77Updated last year
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆86Updated 5 months ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆65Updated 3 years ago
• efabless / clear
  ☆66Updated 6 months ago
• bl0x / learn-fpga-amaranth
  Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
  ☆95Updated 7 months ago
• amaranth-lang / rfcs
  RFCs for changes to the Amaranth language and standard components
  ☆18Updated 5 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆110Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆126Updated last month
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 9 months ago
• fischermoseley / manta
  A configurable and approachable tool for FPGA debugging and rapid prototyping.
  ☆127Updated 2 months ago
• m-labs / nmigen-boards
  Board and connector definition files for nMigen
  ☆30Updated 4 years ago
• amaranth-lang / rtl-debugger
  VS Code based debugger for hardware designs in Amaranth or Verilog
  ☆36Updated 3 months ago
• stnolting / neorv32-setups
  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
  ☆67Updated last week
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆225Updated 4 months ago
• RobertBaruch / amaranth-tutorial
  ☆39Updated 2 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆47Updated last month
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆50Updated last year