Alternatives and similar repositories for amaranth-soc:

Users that are interested in amaranth-soc are comparing it to the libraries listed below

• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 3 years ago
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆112Updated this week
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆28Updated 5 months ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆61Updated last week
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆43Updated 3 months ago
• prjunnamed / prjunnamed
  End-to-end synthesis and P&R toolchain
  ☆78Updated this week
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆79Updated 5 months ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago
• sparrowgrine / prjtritium
  ☆22Updated 3 years ago
• olofk / corescore
  CoreScore
  ☆146Updated 2 months ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 2 years ago
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆87Updated 6 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆111Updated last year
• amaranth-lang / rfcs
  RFCs for changes to the Amaranth language and standard components
  ☆18Updated 6 months ago
• bieganski / mtkcpu
  RISC-V CPU implementation in Amaranth HDL (aka nMigen)
  ☆29Updated 7 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆55Updated last year
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆89Updated 6 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated 10 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆130Updated 2 months ago
• pieter3d / simview
  ☆77Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆45Updated 8 months ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆40Updated 3 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆44Updated 2 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆80Updated 3 weeks ago
• AL-255 / Project-Yatsuhashi-Chip1
  ☆39Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆88Updated 2 weeks ago
• efabless / caravel_board
  ☆33Updated 4 months ago
• amaranth-lang / rtl-debugger
  VS Code based debugger for hardware designs in Amaranth or Verilog
  ☆36Updated 3 months ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆53Updated last year