Alternatives and similar repositories for amaranth-soc:

Users that are interested in amaranth-soc are comparing it to the libraries listed below

• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 3 years ago
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆108Updated last month
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆36Updated 3 years ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆49Updated this week
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆42Updated last month
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆28Updated 3 months ago
• sparrowgrine / prjtritium
  ☆22Updated 2 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 4 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆82Updated 4 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆50Updated last year
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆72Updated 2 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆77Updated 3 months ago
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆85Updated 4 months ago
• amaranth-lang / rtl-debugger
  VS Code based debugger for hardware designs in Amaranth or Verilog
  ☆35Updated last month
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆110Updated last year
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• ECP5-PCIe / ECP5-PCIe
  Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
  ☆94Updated last year
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 2 years ago
• olofk / corescore
  CoreScore
  ☆142Updated this week
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆47Updated 2 weeks ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆125Updated this week
• openXC7 / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆41Updated last month
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 8 months ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆65Updated 3 years ago
• pieter3d / simview
  ☆76Updated 10 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆73Updated this week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆54Updated 3 months ago
• efabless / caravel_board
  ☆33Updated 2 months ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated this week