Alternatives and similar repositories for amaranth-soc

Users that are interested in amaranth-soc are comparing it to the libraries listed below

• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 4 years ago
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆120Updated last month
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆39Updated 3 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆107Updated last month
• olofk / corescore
  CoreScore
  ☆164Updated 2 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆89Updated last week
• ECP5-PCIe / ECP5-PCIe
  Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
  ☆102Updated 2 years ago
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆30Updated last year
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆48Updated 9 months ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆55Updated 3 weeks ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• openXC7 / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆50Updated 4 months ago
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆96Updated last year
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆71Updated 3 years ago
• phanrahan / mantle
  mantle library
  ☆44Updated 2 years ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆57Updated 3 weeks ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆50Updated 9 months ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆77Updated last week
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆80Updated 3 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆48Updated 4 months ago
• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆61Updated last month
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 6 months ago
• prjunnamed / prjunnamed
  End-to-end synthesis and P&R toolchain
  ☆89Updated last month
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆61Updated 2 weeks ago
• m-labs / nmigen-boards
  Board and connector definition files for nMigen
  ☆30Updated 5 years ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• openXC7 / toolchain-installer
  Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7
  ☆90Updated 3 months ago
• fischermoseley / manta
  A configurable and approachable tool for FPGA debugging and rapid prototyping.
  ☆140Updated 6 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆88Updated last week