jeras / fpga-hdlLinks
A set of small Verilog projects, to simulate and implement on FPGA development boards
☆13Updated 7 years ago
Alternatives and similar repositories for fpga-hdl
Users that are interested in fpga-hdl are comparing it to the libraries listed below
Sorting:
- Reusable Verilog 2005 components for FPGA designs☆45Updated 5 months ago
- simple hyperram controller☆12Updated 6 years ago
- ☆20Updated 3 years ago
- USB virtual model in C++ for Verilog☆31Updated 9 months ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆29Updated 5 years ago
- WISHBONE Builder☆14Updated 8 years ago
- Quickly update a bitstream with new RAM contents☆15Updated 4 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆19Updated 3 weeks ago
- Python script for controlling the debug-jtag port of riscv cores☆14Updated 4 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆36Updated 4 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Updated 6 years ago
- A collection of SPI related cores☆17Updated 8 months ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 4 years ago
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Updated 10 years ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆21Updated 5 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- Example Verilog code for Ulx3s☆41Updated 3 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- JTAG DPI module for OpenRISC simulation with Verilator☆17Updated 12 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆43Updated 4 years ago
- DDR3 controller for nMigen (WIP)☆14Updated last year
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆56Updated 2 years ago
- SpinalHDL USB system for the ULPI based Arrow DECA board☆20Updated 3 years ago
- A configurable USB 2.0 device core☆31Updated 5 years ago
- SDRAM controller with multiple wishbone slave ports☆29Updated 6 years ago
- Template Verilator project for beginners☆12Updated 2 years ago
- Nitro USB FPGA core☆87Updated last year
- Simplified environment for litex☆14Updated 4 years ago
- Mini CPU design with JTAG UART support☆20Updated 4 years ago
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆27Updated 3 years ago