Alternatives and similar repositories for fpga-hdl:

Users that are interested in fpga-hdl are comparing it to the libraries listed below

• HarmonInstruments / verilog
  ☆20Updated 2 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆40Updated last year
• freecores / wb_builder
  WISHBONE Builder
  ☆14Updated 8 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆29Updated 4 months ago
• skristiansson / wb_sdram_ctrl
  SDRAM controller with multiple wishbone slave ports
  ☆28Updated 6 years ago
• gtjennings1 / UPDuino-LH154Q01-Display
  Design to connect Lattice Ultraplus FPGA to LH154Q01 Display
  ☆28Updated 6 years ago
• Juninho99 / FPGA_TangNano20k_Hand_Coded_DIP_LCD_Camera
  Master-thesis-final
  ☆18Updated last year
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆25Updated 4 years ago
• tomverbeure / fpga_quick_ram_update
  Quickly update a bitstream with new RAM contents
  ☆15Updated 3 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆38Updated last week
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆40Updated 4 years ago
• Wren6991 / HyperRam
  simple hyperram controller
  ☆11Updated 6 years ago
• juliancoy / openStreamHDL
  VHDL Code for infrastructural blocks (designed for FPGA)
  ☆14Updated 2 years ago
• tinylabs / tinylabs-cores
  Fusesoc compatible rtl cores
  ☆15Updated 2 years ago
• tmeissner / gatemate_experiments
  Experiments with Cologne Chip's GateMate FPGA architecture
  ☆15Updated last year
• FarisHijazi / LZ4-Decompressor-Verilog
  Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language
  ☆14Updated 6 years ago
• umarcor / hwstudio
  GUI editor for hardware description designs
  ☆27Updated last year
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆20Updated last year
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆31Updated 3 years ago
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆22Updated 4 months ago
• ZipCPU / wbspi
  A collection of SPI related cores
  ☆15Updated 3 months ago
• AngeloJacobo / FPGA_SDRAM_Controller
  SDRAM controller optimized to a memory bandwidth of 316MB/s
  ☆25Updated 3 years ago
• davidcastells / py4hw
  Hardware Design/Visualization/Simulation/RTLGeneration Framework
  ☆12Updated 3 weeks ago
• krabo0om / pauloBlaze
  A plain VHDL implementation of a small microprocessor fully compatible with the ISA of the well known PicoBlaze by Ken Chapman.
  ☆22Updated 3 years ago
• Blinkinlabs / QL-EOS-S3-breakout
  ☆12Updated 3 years ago
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆40Updated 2 years ago
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆20Updated 5 years ago
• michg / pyocdriscv32
  Python script for controlling the debug-jtag port of riscv cores
  ☆14Updated 3 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆61Updated 6 years ago
• tomverbeure / ecp5_jtag
  Use ECP5 JTAG port to interact with user design
  ☆26Updated 3 years ago