jeras / fpga-hdl
A set of small Verilog projects, to simulate and implement on FPGA development boards
☆13Updated 6 years ago
Alternatives and similar repositories for fpga-hdl:
Users that are interested in fpga-hdl are comparing it to the libraries listed below
- ☆20Updated 2 years ago
- Reusable Verilog 2005 components for FPGA designs☆39Updated last year
- Wishbone interconnect utilities☆38Updated 7 months ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆59Updated 6 years ago
- SDRAM controller with multiple wishbone slave ports☆28Updated 6 years ago
- Quickly update a bitstream with new RAM contents☆15Updated 3 years ago
- WISHBONE Builder☆14Updated 8 years ago
- JTAG DPI module for OpenRISC simulation with Verilator☆17Updated 12 years ago
- This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…☆18Updated 10 months ago
- Python script for controlling the debug-jtag port of riscv cores☆14Updated 3 years ago
- USB virtual model in C++ for Verilog☆28Updated 3 months ago
- Ethernet MAC 10/100 Mbps☆24Updated 3 years ago
- Template Verilator project for beginners☆12Updated last year
- simple hyperram controller☆11Updated 5 years ago
- 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.☆22Updated 3 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆24Updated 4 years ago
- USB Full Speed PHY☆39Updated 4 years ago
- Fusesoc compatible rtl cores☆15Updated 2 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆40Updated 4 years ago
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- Verilog Repository for GIT☆31Updated 3 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆12Updated 6 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆19Updated 5 years ago
- ULPI Link Wrapper (USB Phy Interface)☆25Updated 4 years ago
- SpinalHDL USB system for the ULPI based Arrow DECA board☆19Updated 3 years ago
- turbo 8051☆28Updated 7 years ago
- SystemC to Verilog Synthesizable Subset Translator☆9Updated last year
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 6 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆50Updated last year