A set of small Verilog projects, to simulate and implement on FPGA development boards
☆15Mar 5, 2018Updated 8 years ago
Alternatives and similar repositories for fpga-hdl
Users that are interested in fpga-hdl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SocKit 1-wire (onewire) master☆19Aug 5, 2012Updated 13 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- An experimental CPU core with 8-bit instruction words and 32-bit registers☆19Jun 1, 2025Updated 10 months ago
- Arduino AltSoftSerial with attachInterrupt for RX chars☆16Apr 17, 2018Updated 7 years ago
- Reusable Verilog 2005 components for FPGA designs☆51Dec 14, 2025Updated 4 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Simple preemptive, realtime, multitask kernel made just for fun.☆11Jul 2, 2020Updated 5 years ago
- FPGA Projects written using SystemVerilog, Verilog, and VHDL are put here in seperate folders.☆19Apr 26, 2017Updated 8 years ago
- Simple Gtkmm in-car computer for Raspberry Pi☆10Jul 8, 2024Updated last year
- Contains all code I use in my PragPub articles☆34Dec 30, 2019Updated 6 years ago
- OpenGL-like graphics pipeline on a Xilinx FPGA☆34Dec 14, 2010Updated 15 years ago
- ☆65Nov 16, 2013Updated 12 years ago
- ☆20Jun 18, 2022Updated 3 years ago
- "I'm not interested in possible complexities. I regard song structure as a graph paper." ― Brian Eno☆33Nov 22, 2019Updated 6 years ago
- Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation☆12Aug 8, 2019Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆26May 12, 2020Updated 5 years ago
- Fullsearch based Motion Estimation Processor written in Verilog-HDL☆11Feb 19, 2017Updated 9 years ago
- Acceleration for an s-curve shaped speed☆12Jun 19, 2024Updated last year
- Numerical Run Length Encoding and Arithmetic in Cython☆19Jan 28, 2026Updated 2 months ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆37Jul 1, 2023Updated 2 years ago
- Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.☆16Jan 10, 2018Updated 8 years ago
- Python framework to solve crypto problems using grainofsalt and cryptominisat☆15May 24, 2022Updated 3 years ago
- A safe immutable string format for C☆14Oct 18, 2025Updated 5 months ago
- vscode support for chez shame☆10Dec 3, 2019Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- 010 Editor Keygen☆16May 14, 2018Updated 7 years ago
- FuseSoC standard core library☆161Mar 11, 2026Updated last month
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆56Jun 11, 2023Updated 2 years ago
- PC sampling profiler for Cortex-M MCUs☆13Jan 23, 2026Updated 2 months ago
- ☆14Oct 6, 2023Updated 2 years ago
- From datasheet (pdf) to SVD... to then be fed into svd2rust☆10May 26, 2022Updated 3 years ago
- DSP Blocks for the nMigen (Python) Toolbox☆11Nov 5, 2020Updated 5 years ago
- Priority queue for C☆12Mar 28, 2023Updated 3 years ago
- ☆15Mar 9, 2026Updated last month
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Legacy Source Code for Dragino Yun firmware with ver 1.3.x☆16Jan 16, 2015Updated 11 years ago
- CppUnit unit testing library☆20Mar 29, 2020Updated 6 years ago
- Embedded facial recognition system involving PYNQ board, Webcam, and HDMI output.☆11May 10, 2018Updated 7 years ago
- Diablo build for BigEndian and SDL1.2 systems☆10Sep 15, 2020Updated 5 years ago
- FPGA implementation of a CDR targeting a Xilinx Kintex-7 for data rates up to 250 MHz☆19Nov 15, 2021Updated 4 years ago
- Simple pin assignment generator for IC case☆19Feb 14, 2017Updated 9 years ago
- A sort-of continuation of the TinyScheme project by Dimitrios Souflis☆13Mar 8, 2016Updated 10 years ago