A set of small Verilog projects, to simulate and implement on FPGA development boards
☆15Mar 5, 2018Updated 8 years ago
Alternatives and similar repositories for fpga-hdl
Users that are interested in fpga-hdl are comparing it to the libraries listed below
Sorting:
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- SocKit 1-wire (onewire) master☆19Aug 5, 2012Updated 13 years ago
- Reusable Verilog 2005 components for FPGA designs☆49Dec 14, 2025Updated 2 months ago
- An experimental CPU core with 8-bit instruction words and 32-bit registers☆19Jun 1, 2025Updated 9 months ago
- ☆20Jun 18, 2022Updated 3 years ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆35Jul 1, 2023Updated 2 years ago
- Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation☆12Aug 8, 2019Updated 6 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 4 years ago
- Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster☆11Oct 14, 2021Updated 4 years ago
- Arduino TFTLCD library for ST7781☆14May 1, 2015Updated 10 years ago
- FuseSoC standard core library☆155Updated this week
- ☆10Jul 30, 2020Updated 5 years ago
- Example project for the BRS-100-GW1NR9 FPGA development board.☆14Feb 14, 2026Updated 3 weeks ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- FDTD 3D simulator that generates s-parameters from OFF geometry files using one or more GPUs☆15Jan 16, 2023Updated 3 years ago
- PC sampling profiler for Cortex-M MCUs☆13Jan 23, 2026Updated last month
- ROACH2 hardware gerbers, layout and bom☆11May 31, 2013Updated 12 years ago
- Python implementation of a simple neural network, including AND, OR, and XOR demos.☆11Jun 13, 2019Updated 6 years ago
- ☆18Jan 19, 2026Updated last month
- repo for CIS 371 Spring 2018☆15Apr 14, 2018Updated 7 years ago
- This is a SpyDrNet Plugin for a physical design related transformations☆16Jun 13, 2025Updated 8 months ago
- ☆14Feb 3, 2025Updated last year
- Python framework to solve crypto problems using grainofsalt and cryptominisat☆14May 24, 2022Updated 3 years ago
- Top level for the November shuttle☆12Nov 20, 2021Updated 4 years ago
- ☆11Oct 24, 2020Updated 5 years ago
- Embedded facial recognition system involving PYNQ board, Webcam, and HDMI output.☆11May 10, 2018Updated 7 years ago
- ☆14Feb 23, 2026Updated last week
- Diablo build for BigEndian and SDL1.2 systems☆10Sep 15, 2020Updated 5 years ago
- An open silicon CHERIoT Ibex microcontroller chip☆18May 23, 2025Updated 9 months ago
- A single-script repo for a script to turn a calibre layer file to a KLayout .lyp file☆13Sep 3, 2018Updated 7 years ago
- stm32的USB-DFU上位机工具源码(MFC)，基于ST官方DfuSe-v3.0.4 ,实现了hex转dfu，解决官方代码的一些bug☆13Aug 9, 2017Updated 8 years ago
- glsl-like scripting language for rapid prototyping of multipass rendering techniques☆13Feb 10, 2026Updated 3 weeks ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- vscode support for chez shame☆10Dec 3, 2019Updated 6 years ago
- This is about the implementation of (2,1,4) Convolutional Encoder and Viterbi Decoder using Verilog VHDL.☆13Aug 12, 2020Updated 5 years ago
- Fault Injection Automatic Test Equipment☆16Nov 22, 2021Updated 4 years ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆11Sep 23, 2022Updated 3 years ago
- DSP Blocks for the nMigen (Python) Toolbox☆11Nov 5, 2020Updated 5 years ago
- A safe immutable string format for C☆14Oct 18, 2025Updated 4 months ago