Martoni / HdmiCoreLinks
HDMI core in Chisel HDL
☆51Updated last year
Alternatives and similar repositories for HdmiCore
Users that are interested in HdmiCore are comparing it to the libraries listed below
Sorting:
- Portable HyperRAM controller☆58Updated 8 months ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆91Updated 7 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆92Updated 5 years ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆32Updated 2 years ago
- SoftCPU/SoC engine-V☆54Updated 5 months ago
- Reusable Verilog 2005 components for FPGA designs☆46Updated 6 months ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi…☆104Updated this week
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 4 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆59Updated 2 years ago
- Another tiny RISC-V implementation☆58Updated 4 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- Example Verilog code for Ulx3s☆41Updated 3 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- PicoRV☆44Updated 5 years ago
- Minimal DVI / HDMI Framebuffer☆83Updated 5 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆66Updated last week
- Miscellaneous ULX3S examples (advanced)☆78Updated 2 months ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 3 years ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆87Updated 2 months ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆80Updated last year
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆62Updated 6 years ago
- Wishbone interconnect utilities☆41Updated 6 months ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆43Updated 4 years ago
- ☆70Updated last year
- Spen's Official OpenOCD Mirror☆50Updated 5 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆105Updated this week
- A tiny POWER Open ISA soft processor written in Chisel☆110Updated 2 years ago
- A pipelined RISC-V processor☆57Updated last year