Alternatives and similar repositories for HdmiCore

Users that are interested in HdmiCore are comparing it to the libraries listed below

• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆91Updated 7 years ago
• MJoergen / HyperRAM
  Portable HyperRAM controller
  ☆59Updated 10 months ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆94Updated 5 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆80Updated 5 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 6 months ago
• nand2mario / ddr3-tang-primer-20k
  DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.
  ☆60Updated 2 years ago
• splinedrive / my_hdmi_device
  New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi…
  ☆105Updated last month
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆32Updated 2 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• ZiyangYE / General-Slow-DDR3-Interface
  A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
  ☆38Updated last year
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆42Updated 8 months ago
• efabless / clear
  ☆70Updated last year
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆47Updated 7 months ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆50Updated 7 months ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆82Updated 5 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆59Updated 4 years ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆29Updated 5 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆81Updated last year
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆42Updated 3 years ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆54Updated 3 weeks ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆90Updated 6 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 6 years ago
• openXC7 / toolchain-installer
  Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7
  ☆90Updated 3 months ago
• emard / ulx3s-misc
  Miscellaneous ULX3S examples (advanced)
  ☆80Updated 3 months ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆39Updated 3 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆88Updated 2 months ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆67Updated last month
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago