Martoni / HdmiCoreLinks
HDMI core in Chisel HDL
☆53Updated last year
Alternatives and similar repositories for HdmiCore
Users that are interested in HdmiCore are comparing it to the libraries listed below
Sorting:
- Portable HyperRAM controller☆62Updated last year
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆93Updated 7 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆97Updated 5 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆66Updated 2 years ago
- New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi…☆105Updated 5 months ago
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆83Updated 5 years ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆91Updated 7 months ago
- Example Verilog code for Ulx3s☆41Updated 3 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆46Updated 5 years ago
- ☆72Updated last year
- RISC-V Processor written in Amaranth HDL☆39Updated 4 years ago
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆103Updated 2 years ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆35Updated 2 years ago
- Spen's Official OpenOCD Mirror☆51Updated 10 months ago
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Updated 7 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆71Updated 3 years ago
- Re-coded Gowin GW1N primitives for Verilator use☆21Updated 3 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 4 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆77Updated last week
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆32Updated 5 years ago
- Miscellaneous ULX3S examples (advanced)☆82Updated 7 months ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- ☆54Updated 3 years ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Minimal DVI / HDMI Framebuffer☆83Updated 5 years ago
- Repo that shows how to use the VexRiscv with OpenOCD and semihosting.☆26Updated 3 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆86Updated last year
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆33Updated last year