austinharris / gem5-riscv
☆12Updated 9 years ago
Alternatives and similar repositories for gem5-riscv:
Users that are interested in gem5-riscv are comparing it to the libraries listed below
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆23Updated 2 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated last week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆10Updated 6 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆23Updated 5 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆17Updated 6 years ago
- Provides dot visualizations of chisel/firrtl circuites☆12Updated 5 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 5 years ago
- A vector processor implemented in Chisel☆21Updated 10 years ago
- Memory consistency model checking and test generation library.☆14Updated 8 years ago
- The RTL source for AnyCore RISC-V☆31Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated 4 months ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 7 months ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆28Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- ☆16Updated 6 years ago
- RTLCheck☆19Updated 6 years ago
- A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.☆22Updated last year
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆19Updated 4 months ago
- This simulator models multi core systems, intended primarily for studies on main memory management techniques. It models a trace-based ou…☆10Updated 9 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- Exploring Shared Virtual Memory Abstractions in OpenCL Tools for FPGAs☆18Updated 7 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 5 months ago
- RISC-V soft-core PEs for TaPaSCo☆18Updated 8 months ago