Alternatives and similar repositories for aetherling:

Users that are interested in aetherling are comparing it to the libraries listed below

• David-Durst / embeddedHaskellAetherling
  ☆25Updated 2 years ago
• vegaluisjose / reticle
  ☆40Updated 3 years ago
• Ekdohibs / PolyGen
  PolyGen is a code generator for the polyhedral model, written and proved in Coq.
  ☆10Updated 4 years ago
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 3 years ago
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆53Updated 4 months ago
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆37Updated last month
• CakeML / hardware
  Verilog development and verification project for HOL4
  ☆24Updated 2 months ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆20Updated last year
• vegaluisjose / reticle-evaluation
  Reticle evaluation (PLDI 2021)
  ☆12Updated 3 years ago
• ymherklotz / vericert
  A formally verified high-level synthesis tool based on CompCert and written in Coq.
  ☆88Updated 6 months ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆63Updated 4 years ago
• rsnikhil / Bluespec_BSV_Formal_Semantics
  Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document
  ☆18Updated 8 years ago
• jameshegarty / rigel
  Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…
  ☆56Updated 4 years ago
• GaloisInc / grift
  Galois RISC-V ISA Formal Tools
  ☆55Updated last year
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆44Updated last year
• upscale-project / generic-sqed-demo
  ☆12Updated 3 years ago
• yihozhang / relational-ematching-benchmark
  ☆16Updated 3 years ago
• cdonovick / peak
  Peak : Processor Specification Language ala Newell and Bell's ISP
  ☆20Updated last year
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated last year
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆138Updated 6 months ago
• johnwickerson / memalloy
  Memory consistency modelling using Alloy
  ☆28Updated 4 years ago
• project-oak / silveroak
  Formal specification and verification of hardware, especially for security and privacy.
  ☆123Updated 2 years ago
• braibant / Synthesis
  ☆21Updated 9 years ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• adamwalker / clash-riscv
  A RiscV processor implementing the RV32I instruction set written in Clash
  ☆51Updated 6 years ago
• sifive / RiscvSpecFormal
  The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, mod…
  ☆75Updated 4 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆24Updated 2 years ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆75Updated 6 months ago
• SiliconSemantics / firrtlator
  firrtlator is a FIRRTL C++ library
  ☆21Updated 8 years ago
• mit-plv / riscv-semantics
  A formal semantics of the RISC-V ISA in Haskell
  ☆160Updated last year