David-Durst / aetherlingLinks
Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python
☆13Updated 4 years ago
Alternatives and similar repositories for aetherling
Users that are interested in aetherling are comparing it to the libraries listed below
Sorting:
- ☆30Updated 3 years ago
- ☆40Updated 4 years ago
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆97Updated last week
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 4 years ago
- The source code to the Voss II Hardware Verification Suite☆56Updated this week
- FPGA synthesis tool powered by program synthesis☆54Updated last month
- Time-sensitive affine types for predictable hardware generation☆148Updated last month
- Memory consistency modelling using Alloy☆31Updated 5 years ago
- Verilog development and verification project for HOL4☆28Updated 9 months ago
- A pure, low-level tensor program representation enabling tensor program optimization via program rewriting. See the web demo at https://g…☆72Updated 8 months ago
- BTOR2 MLIR project☆26Updated 2 years ago
- Formal specification and verification of hardware, especially for security and privacy.☆128Updated 3 years ago
- Scala staging framework☆18Updated 7 years ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆57Updated 5 years ago
- Automatically generate a compiler using equality saturation☆34Updated last year
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆164Updated 2 months ago
- Verilog AST☆21Updated 2 years ago
- A standard for floating point accuracy benchmarks☆58Updated 3 weeks ago
- A core language for rule-based hardware design 🦑☆171Updated last month
- ☆16Updated 4 years ago
- work in progress, playing around with btor2 in rust☆12Updated last week
- RTLCheck☆24Updated 7 years ago
- CoreIR Symbolic Analyzer☆74Updated 5 years ago
- benchmarking e-graph extraction☆49Updated last week
- A Hardware Pipeline Description Language☆49Updated 6 months ago
- Manythread RISC-V overlay for FPGA clusters☆39Updated 4 months ago
- The implementation of the Elevate language☆30Updated 10 months ago
- sketches for egg: a flexible, high-performance e-graph library☆30Updated 4 months ago
- Search-based compiler for high-performance DSP programming☆71Updated last year
- ☆13Updated 5 years ago