David-Durst / aetherling
Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python
☆13Updated 4 years ago
Alternatives and similar repositories for aetherling:
Users that are interested in aetherling are comparing it to the libraries listed below
- ☆25Updated 2 years ago
- ☆40Updated 3 years ago
- PolyGen is a code generator for the polyhedral model, written and proved in Coq.☆10Updated 4 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- FPGA synthesis tool powered by program synthesis☆42Updated this week
- A Hardware Pipeline Description Language☆44Updated last year
- Verilog AST☆21Updated last year
- The source code to the Voss II Hardware Verification Suite☆56Updated 2 weeks ago
- Memory consistency modelling using Alloy☆29Updated 4 years ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 4 years ago
- BTOR2 MLIR project☆25Updated last year
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆91Updated 10 months ago
- FPGA-based HyperLogLog Accelerator☆12Updated 4 years ago
- A toy compiler for NumPy array expressions that uses e-graphs and MLIR☆42Updated this week
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 8 years ago
- Manythread RISC-V overlay for FPGA clusters☆38Updated 2 years ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆10Updated 10 months ago
- Time-sensitive affine types for predictable hardware generation☆143Updated 9 months ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year
- CHERI-RISC-V model written in Sail☆58Updated 3 weeks ago
- ☆55Updated 2 years ago
- A Language for Closed-form High-level ARchitecture Modeling☆20Updated 5 years ago
- compiling DSLs to high-level hardware instructions☆22Updated 2 years ago
- Peak : Processor Specification Language ala Newell and Bell's ISP☆20Updated last year
- A pure, low-level tensor program representation enabling tensor program optimization via program rewriting. See the web demo at https://g…☆70Updated 10 months ago
- ☆13Updated 4 years ago
- firrtlator is a FIRRTL C++ library☆21Updated 8 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆35Updated last month
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆21Updated this week
- CoreIR Symbolic Analyzer☆72Updated 4 years ago