jianyicheng / HLS-benchmarks

Related projects: ⓘ

• Junyi-Liu / benchmarks-HLS
  Benchmarks, testbenches, and transformed codes for high-level synthesis research
  ☆13Updated 7 years ago
• CMU-SAFARI / CLRDRAM
  Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…
  ☆12Updated 3 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆38Updated 4 years ago
• maltanar / spmvaccsim
  A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.
  ☆13Updated 9 years ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆29Updated 2 years ago
• hyoukjun / microswitch-noc
  ☆21Updated 4 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆44Updated 7 years ago
• wincle626 / HLS_Legup
  ☆24Updated 6 years ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆41Updated 3 years ago
• Reconfigurable-Computing / HLStoFPGA
  ☆12Updated 2 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆28Updated 8 years ago
• A-T-Kristensen / patmos_HLS
  Hardware Accelerators (HwAs) constructed in Vivado HLS
  ☆17Updated 7 years ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆26Updated 11 months ago
• StanfordVLSI / FP-Gen
  FPU Generator
  ☆18Updated 3 years ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆18Updated 3 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆24Updated 4 years ago
• IBM / esp-chisel-accelerators
  Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
  ☆23Updated 4 years ago
• icgrp / hipr
  ☆11Updated last year
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆27Updated 3 years ago
• gjlies / configgpgpu
  A configurable general purpose graphics processing unit for
  ☆11Updated 5 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆19Updated 2 years ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆15Updated 5 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆56Updated 3 years ago
• PacoReinaCampo / MPSoC-NoC
  Network on Chip for MPSoC
  ☆24Updated this week
• maltanar / systemc-chisel-tools
  A collection of tools for working with Chisel-generated hardware in SystemC
  ☆16Updated 5 years ago
• momalab / CoPHEE
  CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
  ☆25Updated 6 months ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆15Updated 3 months ago
• amin-norollah / PAT-Noxim
  cycle accurate Network-on-Chip Simulator
  ☆24Updated last year
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆36Updated last year
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated last year