jianyicheng / HLS-benchmarksLinks
Benchmarks for High-Level Synthesis
☆10Updated 2 years ago
Alternatives and similar repositories for HLS-benchmarks
Users that are interested in HLS-benchmarks are comparing it to the libraries listed below
Sorting:
- ☆29Updated 8 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 8 years ago
- ☆12Updated 3 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 8 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆42Updated this week
- LIS Network-on-Chip Implementation☆31Updated 9 years ago
- Hardware Accelerators (HwAs) constructed in Vivado HLS☆20Updated 8 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆35Updated 2 months ago
- A tool to generate optimized hardware files for univariate functions.☆28Updated last year
- RISC-V soft-core PEs for TaPaSCo☆22Updated last year
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆114Updated last year
- ASIC Design kit for Skywater 130 for use with mflowgen☆13Updated 2 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- DDR4 Simulation Project in System Verilog☆41Updated 11 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Updated 5 years ago
- StateMover is a checkpoint-based debugging framework for FPGAs.☆20Updated 3 years ago
- ☆30Updated 3 weeks ago
- A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …☆31Updated last year
- ILA Model Database☆23Updated 5 years ago
- Original test vector of RISC-V Vector Extension☆14Updated 4 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago