wvangansbeke / High-Level-SynthesisLinks
Convert C files into Verilog
☆17Updated 6 years ago
Alternatives and similar repositories for High-Level-Synthesis
Users that are interested in High-Level-Synthesis are comparing it to the libraries listed below
Sorting:
- ☆27Updated 7 years ago
- The PE for the second generation CGRA (garnet).☆17Updated 2 months ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)☆22Updated 4 years ago
- Hardware Formal Verification☆15Updated 4 years ago
- Polyhedral Compilation tool for High Level Synthesis.☆10Updated 11 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 10 months ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- GL0AM GPU Accelerated Gate Level Logic Simulator☆22Updated 2 weeks ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 5 months ago
- EDA Analytics Central☆16Updated 2 years ago
- Macro placement tool for OpenROAD flow☆23Updated 4 years ago
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆13Updated 8 years ago
- Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout☆12Updated 11 years ago
- OpenDesign Flow Database☆16Updated 6 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 4 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- FPGA acceleration of arbitrary precision floating point computations.☆40Updated 3 years ago
- RTLCheck☆22Updated 6 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated last month
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Updated 4 years ago
- C++17 implementation of an AST for Verilog code generation☆24Updated 2 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last month
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 2 years ago
- ☆17Updated this week
- ☆15Updated 4 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆60Updated 3 years ago