Alternatives and similar repositories for High-Level-Synthesis

Users that are interested in High-Level-Synthesis are comparing it to the libraries listed below

• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 8 months ago
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆40Updated 3 years ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆32Updated 2 years ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆34Updated 7 months ago
• wincle626 / HLS_Legup
  ☆29Updated 8 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆68Updated 10 months ago
• yzwangfeng / reram-synthesis
  A synthesis flow for hybrid processing-in-RRAM modes
  ☆12Updated 4 years ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆24Updated 4 years ago
• shalan / AD_SAR_ADC
  Digital Standard Cells based SAR ADC
  ☆14Updated 4 years ago
• ben-marshall / verilog-dot
  A simple dot file / graph generator for Verilog syntax trees.
  ☆23Updated 9 years ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆116Updated last year
• StanfordVLSI / DaVE
  tools regarding on analog modeling, validation, and generation
  ☆22Updated 2 years ago
• pulp-platform / redmule
  ☆90Updated 2 weeks ago
• cornell-brg / pymtl-tut-hls
  Tutorial for integrating PyMTL and Vivado HLS
  ☆19Updated 9 years ago
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆17Updated 5 years ago
• bespoke-silicon-group / bsg_replicant
  BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
  ☆37Updated 4 months ago
• pulp-platform / ELAU
  ☆20Updated last year
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• jianyicheng / HLS-benchmarks
  Benchmarks for High-Level Synthesis
  ☆10Updated 2 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• daitoto / EDA-wiki
  EDA wiki
  ☆53Updated 2 years ago
• icgrp / hipr
  ☆17Updated 2 years ago
• nkkav / yosys-examples
  Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)
  ☆22Updated 4 years ago
• ic-lab-duth / Fast-Float4HLS
  Fast Floating Point Operators for High Level Synthesis
  ☆23Updated 2 years ago
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆35Updated 3 weeks ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆32Updated last year
• ic-lab-duth / DRIM4HLS
  DUTH RISC V Microprocessor for High Level Synthesis
  ☆10Updated 2 years ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆114Updated 2 years ago
• taneroksuz / mult-tree
  Wallace and Dadda tree multiplier generator in vhdl and verilog
  ☆11Updated last year