wvangansbeke / High-Level-SynthesisView external linksLinks
Convert C files into Verilog
☆20Jan 27, 2019Updated 7 years ago
Alternatives and similar repositories for High-Level-Synthesis
Users that are interested in High-Level-Synthesis are comparing it to the libraries listed below
Sorting:
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- A copy of the latest version of MVSIS☆12Apr 18, 2021Updated 4 years ago
- c++ version of ViT☆12Nov 13, 2022Updated 3 years ago
- ☆11Jul 1, 2025Updated 7 months ago
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆13Mar 27, 2025Updated 10 months ago
- Python Verilog-AMS Parser☆12Oct 13, 2015Updated 10 years ago
- A fork of Yosys that integrates the CellIFT pass☆13Jul 23, 2025Updated 6 months ago
- Parallel SAT Solver☆10Jan 19, 2018Updated 8 years ago
- CUDA program to find the tallest possible cacti in Minecraft.☆10Jan 1, 2024Updated 2 years ago
- ☆10Oct 15, 2021Updated 4 years ago
- A collection of URLs related to High Level Synthesis (HLS).☆13Jun 26, 2021Updated 4 years ago
- Benchmarks for High-Level Synthesis☆10Mar 17, 2023Updated 2 years ago
- ☆14Jan 3, 2018Updated 8 years ago
- ☆14Jun 18, 2023Updated 2 years ago
- SPICE based IBIS simulation☆16Jan 2, 2025Updated last year
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 6 years ago
- Development of a virtual quadruped robot using OpenAI & Mujoco☆17Feb 15, 2023Updated 2 years ago
- Gate-Level Simulation on a GPU☆10Nov 22, 2016Updated 9 years ago
- Semi-Tenser Product based SAT and AllSAT solver, where it can solve CNF and circuit input.☆17Aug 2, 2023Updated 2 years ago
- Digital Standard Cells based SAR ADC☆14Aug 5, 2021Updated 4 years ago
- ☆15Apr 26, 2021Updated 4 years ago
- Python version of tools to work with AIG formatted files☆12May 20, 2025Updated 8 months ago
- Integration and Supervisory control of Autonomous Robots☆19Updated this week
- ☆15Dec 30, 2025Updated last month
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆18Nov 1, 2022Updated 3 years ago
- Arbitrary Cell Generator enables parametrized grid-free circuit layout creation☆17Jun 1, 2020Updated 5 years ago
- Qute: a dependency learning QBF solver.☆14Dec 19, 2025Updated last month
- Code for the NeurIPS 2020 paper Efficient Exact Verification of Binarized Neural Networks☆13Jun 30, 2022Updated 3 years ago
- An LLVM based mini-C to Verilog High-level Synthesis tool☆39Mar 7, 2025Updated 11 months ago
- A hardware model checker for hyperproperties☆18Jun 14, 2024Updated last year
- CV32E40X Design-Verification environment☆16Mar 25, 2024Updated last year
- ☆15Nov 9, 2022Updated 3 years ago
- Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"☆15Sep 12, 2022Updated 3 years ago
- Combination of Analog Circuit Sizing and DL.☆18Mar 24, 2023Updated 2 years ago
- ☆16Jan 5, 2022Updated 4 years ago
- symbolic reachability checker☆23Sep 23, 2021Updated 4 years ago
- A Formal Verification Framework for Chisel☆18Apr 9, 2024Updated last year
- Hardware Formal Verification☆17Aug 10, 2020Updated 5 years ago
- LLM4HWDesign Starting Toolkit☆19Oct 4, 2024Updated last year