udif / ctoverilog
A C to verilog compiler
☆49Updated 9 years ago
Related projects ⓘ
Alternatives and complementary repositories for ctoverilog
- The Shang high-level synthesis framework☆119Updated 10 years ago
- An LLVM based mini-C to Verilog High-level Synthesis tool☆35Updated last year
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆54Updated 7 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 4 years ago
- Documentation for the BOOM processor☆47Updated 7 years ago
- A 32-bit RISC-V processor for mriscv project☆56Updated 7 years ago
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆37Updated 2 months ago
- RISC-V Frontend Server☆62Updated 5 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆46Updated 9 years ago
- The BERI and CHERI processor and hardware platform☆46Updated 7 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆54Updated 5 years ago
- A template for building new projects/platforms using the BOOM core.☆24Updated 5 years ago
- A Verilog Synthesis Regression Test☆34Updated 7 months ago
- A fork of the main Verilator project for development work. The changes here are in preparation for committing back to the main project.☆18Updated 9 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆99Updated 5 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- DyRACT Open Source Repository☆16Updated 8 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- A time-predictable processor for mixed-criticality systems☆56Updated this week
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- The OpenRISC 1000 architectural simulator☆71Updated 2 months ago
- ☆29Updated 4 years ago
- Open Processor Architecture☆26Updated 8 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆29Updated 3 years ago
- An executable specification of the RISCV ISA in L3.☆41Updated 5 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 3 months ago
- Torc: Tools for Open Reconfigurable Computing☆39Updated 7 years ago