udif / ctoverilog
A C to verilog compiler
☆52Updated 9 years ago
Alternatives and similar repositories for ctoverilog:
Users that are interested in ctoverilog are comparing it to the libraries listed below
- An LLVM based mini-C to Verilog High-level Synthesis tool☆35Updated 2 months ago
- The Shang high-level synthesis framework☆119Updated 10 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆39Updated 9 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 7 years ago
- Documentation for the BOOM processor☆47Updated 8 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆55Updated 4 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 6 years ago
- A 32-bit RISC-V processor for mriscv project☆58Updated 7 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- DyRACT Open Source Repository☆16Updated 9 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- RISC-V BSV Specification☆20Updated 5 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Updated 4 years ago
- Mutation Cover with Yosys (MCY)☆80Updated this week
- An instruction set simulator based on DBT-RISE implementing the RISC-V ISA☆35Updated last week
- Useful utilities for BAR projects☆31Updated last year
- An online Verilog IDE based on YosysJS.☆24Updated 9 years ago
- RISC-V GPGPU☆34Updated 5 years ago
- SoCRocket - Core Repository☆35Updated 8 years ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- ☆109Updated 6 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆55Updated 5 years ago
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆37Updated 8 months ago
- OpenFPGA☆33Updated 7 years ago
- The OpenRISC 1000 architectural simulator☆74Updated 2 weeks ago
- Simple MIDAS Examples☆12Updated 6 years ago
- Torc: Tools for Open Reconfigurable Computing☆38Updated 8 years ago