A C to verilog compiler
☆52Jun 20, 2015Updated 10 years ago
Alternatives and similar repositories for ctoverilog
Users that are interested in ctoverilog are comparing it to the libraries listed below
Sorting:
- An LLVM based mini-C to Verilog High-level Synthesis tool☆39Mar 7, 2025Updated 11 months ago
- The Shang high-level synthesis framework☆120May 29, 2014Updated 11 years ago
- Software for error-tolerant coding of information into DNA sequences using finite-state transducers.☆12Jan 8, 2017Updated 9 years ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- Netlist and Verilog Haskell Package☆19Nov 21, 2010Updated 15 years ago
- An implementation of the Mixcoin mixing protocol☆13Nov 12, 2014Updated 11 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- Welcome to Birds-of-a-Feather: Open-Source-Academic-EDA-Software !☆14Jun 6, 2019Updated 6 years ago
- ☆10Oct 15, 2021Updated 4 years ago
- Header-only binarycookies parser.☆17Feb 20, 2026Updated last week
- ☆14Sep 14, 2020Updated 5 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Sep 24, 2020Updated 5 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Aug 2, 2019Updated 6 years ago
- Optimal gate sizing of digital circuits using geometric programming☆11Aug 18, 2016Updated 9 years ago
- ☆13Feb 6, 2021Updated 5 years ago
- Gate-Level Simulation on a GPU☆10Nov 22, 2016Updated 9 years ago
- a list of StrongAI related resources.☆11Mar 26, 2023Updated 2 years ago
- Python version of tools to work with AIG formatted files☆12May 20, 2025Updated 9 months ago
- ☆15May 24, 2023Updated 2 years ago
- Symbolic Geometric Algebra with E-Graphs☆19Oct 11, 2023Updated 2 years ago
- ☆15Nov 9, 2022Updated 3 years ago
- We try to put source files of llvm tutorials here☆18Oct 6, 2020Updated 5 years ago
- RISC CPU by Icenowy☆12Dec 26, 2018Updated 7 years ago
- Hardware Formal Verification☆17Aug 10, 2020Updated 5 years ago
- A Formal Verification Framework for Chisel☆18Apr 9, 2024Updated last year
- Convert C files into Verilog☆21Jan 27, 2019Updated 7 years ago
- A fork of the main Verilator project for development work. The changes here are in preparation for committing back to the main project.☆18Nov 26, 2014Updated 11 years ago
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆20Sep 4, 2025Updated 5 months ago
- ☆17Nov 19, 2023Updated 2 years ago
- Cross platform Instant Outbidding Bot, Instant Outbidder Bot is designed to outbid all real-time bids within a second by percentage incre…☆100Jan 17, 2023Updated 3 years ago
- website of hellollvm.org☆39Jun 20, 2025Updated 8 months ago
- Lua parser and pretty-printer☆52May 5, 2016Updated 9 years ago
- ☆18Jul 11, 2021Updated 4 years ago
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Jun 4, 2019Updated 6 years ago
- Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)☆22Apr 28, 2021Updated 4 years ago
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆17Dec 1, 2018Updated 7 years ago
- Torch implementation of SRGAN (Ledig et al., Photo -Realistic Single Image Super-Resolution Using a Generative Adversarial Network, 2016)☆14Nov 17, 2016Updated 9 years ago
- ☆19Jul 12, 2024Updated last year