Alternatives and similar repositories for HLS_Legup

Users that are interested in HLS_Legup are comparing it to the libraries listed below

• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆28Updated last year
• icgrp / hipr
  ☆15Updated 2 years ago
• zslwyuan / Light-HLS
  Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)
  ☆60Updated 3 years ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆23Updated 4 years ago
• Junyi-Liu / benchmarks-HLS
  Benchmarks, testbenches, and transformed codes for high-level synthesis research
  ☆13Updated 7 years ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• jasonlin316 / Systolic-Array-for-Smith-Waterman
  This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …
  ☆26Updated 6 years ago
• pku-dasys / cocoon
  An infrastructure for integrated EDA
  ☆41Updated last year
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆50Updated 8 years ago
• Xilinx / merlin-compiler
  ☆58Updated last year
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 2 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 5 years ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆48Updated 3 months ago
• ucb-bar / gemmini-rocc-tests
  Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
  ☆59Updated 2 weeks ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated last month
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆35Updated 5 months ago
• kumasento / polsca
  Polyhedral High-Level Synthesis in MLIR
  ☆33Updated 2 years ago
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆40Updated 6 months ago
• cornell-zhang / datuner
  DATuner Repository
  ☆18Updated 6 years ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆41Updated 3 weeks ago
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated last year
• amin-norollah / PAT-Noxim
  cycle accurate Network-on-Chip Simulator
  ☆28Updated 2 years ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆112Updated this week
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆32Updated this week
• daitoto / EDA-wiki
  EDA wiki
  ☆54Updated 2 years ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 3 years ago
• jianyicheng / iiProver
  An LLVM pass to prove that an II works for the given loop for Vitis HLS
  ☆11Updated 3 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago