Alternatives and similar repositories for Asynchronous-Verilog-Synthesiser:

Users that are interested in Asynchronous-Verilog-Synthesiser are comparing it to the libraries listed below

• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• sabbaghm / c-ll-verilog
  An LLVM based mini-C to Verilog High-level Synthesis tool
  ☆35Updated 3 weeks ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆23Updated 5 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆22Updated last week
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 5 years ago
• RCSL-HKUST / heterosim
  HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design…
  ☆21Updated 8 years ago
• EDAPack / edapack
  Provides a packaged collection of open source EDA tools
  ☆12Updated 5 years ago
• nkkav / yosys-examples
  Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)
  ☆21Updated 3 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• wvangansbeke / High-Level-Synthesis
  Convert C files into Verilog
  ☆16Updated 6 years ago
• andrewattwood / fuserisc
  Dual RISC-V DISC with integrated eFPGA
  ☆16Updated 3 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆20Updated 7 years ago
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆15Updated 5 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆21Updated last week
• x-epic / EpicFV
  ☆20Updated 4 years ago
• libresilicon / coriolis
  autorouter forked from https://www-soc.lip6.fr/git/coriolis.git
  ☆15Updated 6 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆32Updated 11 months ago
• PacoReinaCampo / PU-RISCV
  Processing Unit with RISCV-32 / RISCV-64 / RISCV-128
  ☆19Updated 2 weeks ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated last week
• pulp-platform / hero-sdk
  ⛔ DEPRECATED ⛔ HERO Software Development Kit
  ☆20Updated 3 years ago
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 5 years ago
• The-OpenROAD-Project / Birds-of-a-Feather-Open-Source-Academic-EDA-Software
  Welcome to Birds-of-a-Feather: Open-Source-Academic-EDA-Software !
  ☆12Updated 5 years ago
• Open-Source-Hardware-Initiative / AES
  Open Source AES
  ☆31Updated 11 months ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• libresilicon / magic-8.2
  Magic VLSI Layout Tool
  ☆21Updated 5 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆16Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago