Alternatives and similar repositories for reticle

Users that are interested in reticle are comparing it to the libraries listed below

• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆145Updated this week
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆52Updated 2 months ago
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆160Updated 3 months ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆45Updated 2 months ago
• ymherklotz / vericert
  A formally verified high-level synthesis tool based on CompCert and written in Coq.
  ☆93Updated last week
• David-Durst / embeddedHaskellAetherling
  ☆26Updated 2 years ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆56Updated last month
• rdaly525 / coreir
  ☆103Updated 3 years ago
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 3 years ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• gussmith23 / glenside
  A pure, low-level tensor program representation enabling tensor program optimization via program rewriting. See the web demo at https://g…
  ☆70Updated 3 months ago
• David-Durst / aetherling
  Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python
  ☆13Updated 4 years ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated 2 years ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆59Updated last year
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 4 years ago
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆108Updated 9 years ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆112Updated 3 months ago
• kumasento / polymer
  Bridging polyhedral analysis tools to the MLIR framework
  ☆116Updated 2 years ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆77Updated last year
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆50Updated 2 years ago
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆36Updated 5 months ago
• CTSRD-CHERI / bluecheck
  A generic test bench written in Bluespec
  ☆54Updated 4 years ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆175Updated last year
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆23Updated 4 years ago
• cornell-zhang / hcl-dialect
  HeteroCL-MLIR dialect for accelerator design
  ☆41Updated 11 months ago
• cucapra / diospyros
  Search-based compiler for high-performance DSP programming
  ☆67Updated 10 months ago
• mit-plv / kami
  A Platform for High-Level Parametric Hardware Specification and its Modular Verification
  ☆158Updated last month
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆27Updated 2 years ago
• CakeML / hardware
  Verilog development and verification project for HOL4
  ☆27Updated 4 months ago