vegaluisjose / reticleLinks
☆40Updated 3 years ago
Alternatives and similar repositories for reticle
Users that are interested in reticle are comparing it to the libraries listed below
Sorting:
- Verilog AST☆21Updated last year
- Time-sensitive affine types for predictable hardware generation☆143Updated 10 months ago
- A Hardware Pipeline Description Language☆44Updated last year
- ☆26Updated 2 years ago
- A pure, low-level tensor program representation enabling tensor program optimization via program rewriting. See the web demo at https://g…☆70Updated 11 months ago
- FPGA synthesis tool powered by program synthesis☆48Updated last week
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆13Updated 4 years ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆49Updated last year
- The source code to the Voss II Hardware Verification Suite☆56Updated last month
- ☆103Updated 2 years ago
- ILA Model Database☆22Updated 4 years ago
- compiling DSLs to high-level hardware instructions☆22Updated 2 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆28Updated 3 months ago
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆92Updated 11 months ago
- BTOR2 MLIR project☆25Updated last year
- A core language for rule-based hardware design 🦑☆154Updated 7 months ago
- A polyhedral compiler for hardware accelerators☆57Updated 10 months ago
- EQueue Dialect☆40Updated 3 years ago
- A Language for Closed-form High-level ARchitecture Modeling☆20Updated 5 years ago
- Bridging polyhedral analysis tools to the MLIR framework☆111Updated last year
- A hardware synthesis framework with multi-level paradigm☆39Updated 4 months ago
- PolyGen is a code generator for the polyhedral model, written and proved in Coq.☆10Updated 4 years ago
- ☆24Updated 4 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last week
- HeteroRefactor: Refactoring for Heterogeneous Computing with FPGA☆10Updated 3 years ago
- ☆41Updated 4 months ago
- ☆15Updated 2 years ago
- A formalization of the RVWMO (RISC-V) memory model☆33Updated 2 years ago