vegaluisjose / reticle
☆40Updated 3 years ago
Alternatives and similar repositories for reticle:
Users that are interested in reticle are comparing it to the libraries listed below
- ☆25Updated 2 years ago
- Verilog AST☆21Updated last year
- A Hardware Pipeline Description Language☆44Updated last year
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year
- Time-sensitive affine types for predictable hardware generation☆142Updated 7 months ago
- ☆102Updated 2 years ago
- A pure, low-level tensor program representation enabling tensor program optimization via program rewriting. See the web demo at https://g…☆71Updated 9 months ago
- The source code to the Voss II Hardware Verification Suite☆57Updated this week
- A core language for rule-based hardware design 🦑☆147Updated 5 months ago
- BTOR2 MLIR project☆25Updated last year
- FPGA synthesis tool powered by program synthesis☆41Updated 3 months ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆12Updated 3 years ago
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆89Updated 8 months ago
- PolyGen is a code generator for the polyhedral model, written and proved in Coq.☆10Updated 4 years ago
- CoreIR Symbolic Analyzer☆64Updated 4 years ago
- A polyhedral compiler for hardware accelerators☆56Updated 7 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆48Updated last year
- Reticle evaluation (PLDI 2021)☆12Updated 3 years ago
- ILA Model Database☆22Updated 4 years ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆95Updated this week
- CHERI-RISC-V model written in Sail☆58Updated last month
- ☆10Updated 2 years ago
- compiling DSLs to high-level hardware instructions☆22Updated 2 years ago
- A Language for Closed-form High-level ARchitecture Modeling☆20Updated 5 years ago
- Manythread RISC-V overlay for FPGA clusters☆35Updated 2 years ago
- A formalization of the RVWMO (RISC-V) memory model☆32Updated 2 years ago
- Bluespec BSV HLHDL tutorial☆101Updated 8 years ago
- Bridging polyhedral analysis tools to the MLIR framework☆109Updated last year
- A hardware synthesis framework with multi-level paradigm☆38Updated 2 months ago