Polyphony is Python based High-Level Synthesis compiler.
☆109Jan 29, 2025Updated last year
Alternatives and similar repositories for polyphony
Users that are interested in polyphony are comparing it to the libraries listed below
Sorting:
- ☆54Jul 25, 2024Updated last year
- Python-based Portable IP-core Synthesis Framework for FPGA-based Computing☆53Nov 21, 2016Updated 9 years ago
- Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…☆108Jan 29, 2022Updated 4 years ago
- Veriloggen: A Mixed-Paradigm Hardware Construction Framework☆325Aug 10, 2024Updated last year
- The Shang high-level synthesis framework☆120May 29, 2014Updated 11 years ago
- IP-core package generator for AXI4/Avalon☆22Nov 25, 2018Updated 7 years ago
- Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)☆35Jul 9, 2021Updated 4 years ago
- ☆24Nov 10, 2020Updated 5 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆18Aug 1, 2019Updated 6 years ago
- ☆12Aug 10, 2018Updated 7 years ago
- soap - Structural Optimisation of Arithmetic Programs☆24May 9, 2016Updated 9 years ago
- a free, portable, minimalist, work-in-progress RTPS implementation☆12Nov 1, 2017Updated 8 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Jun 11, 2024Updated last year
- ☆13Jun 12, 2018Updated 7 years ago
- 株式会社Cerevo 「MKZ4」向けのArduinoソースコード等を集約したリポジトリ☆13Aug 17, 2022Updated 3 years ago
- HOG + SVM on FPGA☆28Dec 16, 2020Updated 5 years ago
- NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network☆361Oct 17, 2023Updated 2 years ago
- Combination of Analog Circuit Sizing and DL.☆18Mar 24, 2023Updated 2 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Jul 23, 2019Updated 6 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆221Dec 23, 2025Updated 2 months ago
- TOPPERSユーザーズフォーラム：ユーザのためのQ&Aおよび情報交換の場☆12Jun 16, 2022Updated 3 years ago
- GUINNESS: A GUI-based binarized deep Neural NEtwork SyntheSizer toward an FPGA☆181Jul 20, 2019Updated 6 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Jul 10, 2019Updated 6 years ago
- A Vivado HLS Command Line Helper Tool☆36Oct 6, 2021Updated 4 years ago
- A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications☆38Oct 20, 2020Updated 5 years ago
- mantle library☆44Dec 20, 2022Updated 3 years ago
- ☆12Dec 22, 2024Updated last year
- Original FPGA platform☆71Feb 5, 2026Updated 3 weeks ago
- Java and Scala client libraries for Concord☆13Feb 15, 2017Updated 9 years ago
- ☆10Jun 10, 2025Updated 8 months ago
- "mmult" example using SDSoC for PYNQ board☆11Feb 23, 2017Updated 9 years ago
- ☆10Jan 15, 2023Updated 3 years ago
- OpenReroc (Open source Reconfigurable robot component)☆10Oct 17, 2016Updated 9 years ago
- A vhdl package for reading and writing bitmap files.☆11Jan 9, 2018Updated 8 years ago
- ☆11May 5, 2015Updated 10 years ago
- Chrome extension to do bulk operation and things not allowed in GraphAPI, such as breaking the filter bubble☆12Feb 28, 2018Updated 8 years ago
- ☆10Jul 7, 2020Updated 5 years ago
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆25Mar 11, 2023Updated 2 years ago
- RISC-V documentation transrate to Japanese.☆73Jan 1, 2022Updated 4 years ago