polyphony-dev / polyphonyLinks
Polyphony is Python based High-Level Synthesis compiler.
☆109Updated last year
Alternatives and similar repositories for polyphony
Users that are interested in polyphony are comparing it to the libraries listed below
Sorting:
- Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…☆107Updated 4 years ago
- Veriloggen: A Mixed-Paradigm Hardware Construction Framework☆324Updated last year
- Binary Neural Network Framework for FPGA(Differentiable LUT)☆171Updated 5 months ago
- Original FPGA platform☆71Updated this week
- Python-based Portable IP-core Synthesis Framework for FPGA-based Computing☆53Updated 9 years ago
- NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network☆360Updated 2 years ago
- Open source RISC-V IP core for FPGA/ASIC design☆32Updated last year
- みんなのSystemVerilog☆19Updated 3 years ago
- The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.☆45Updated 4 years ago
- ☆54Updated last year
- Source Codes for a lecture entitled "Parallel and Reconfigurable VLSI Computing" in Tokyo Tech.☆28Updated 4 years ago
- 10G Ethernet MAC implementation☆23Updated 5 years ago
- Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)☆35Updated 4 years ago
- 「Chiselを始めたい人に読んで欲しい本」のサンプルコード用リポジトリ☆10Updated 4 years ago
- Basic Common Modules☆46Updated last month
- GUINNESS: A GUI-based binarized deep Neural NEtwork SyntheSizer toward an FPGA☆181Updated 6 years ago
- FPGA Magazine No.18 - RISC-V☆18Updated 8 years ago
- FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)☆132Updated 5 months ago
- (under construction) Experimental circuit design for FPGA based PCIe accelerator board providing emulated NVMe/PCIe device that its read/…☆27Updated 3 years ago
- This is my first trial project for designing RISC-V in Chisel☆17Updated last year
- ☆236Updated 2 years ago
- Repository of HW design and SW for Ultra96 board + MIPI board☆17Updated 6 years ago
- An UGV-system using SoC-FPGA developed for FPGA design competition held on ICFPT2019☆18Updated 5 years ago
- ☆16Updated 9 years ago
- RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo☆13Updated 5 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- Implementation VexRiscv on ultra96☆13Updated 3 years ago
- ☆39Updated last year
- FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq-Zybo:PYNQ-Z1 Altera:de0-nano-soc:de1…☆168Updated 2 months ago
- ☆14Updated 6 years ago