Learn NVDLA by SOMNIA
☆42Dec 13, 2019Updated 6 years ago
Alternatives and similar repositories for somnia
Users that are interested in somnia are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆235Dec 22, 2025Updated 3 months ago
- ☆49Nov 18, 2019Updated 6 years ago
- NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…☆232Dec 18, 2018Updated 7 years ago
- This is Max's blog, something interesting in it.☆13Jan 1, 2023Updated 3 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated last month
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆61Mar 14, 2022Updated 4 years ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆25Mar 8, 2026Updated 2 weeks ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆22Apr 25, 2025Updated 11 months ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆167Jan 16, 2022Updated 4 years ago
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 9 months ago
- A NVDLA Loadable Parser.☆12Mar 2, 2022Updated 4 years ago
- OpenDLA for trying the demo and FPGA solution☆17Jul 28, 2022Updated 3 years ago
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- This is the open-source version of TinyTS. The code is dirty so far. We may clean the code in the future.☆20Aug 11, 2025Updated 7 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- ☆22Nov 3, 2025Updated 4 months ago
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- PyTorch compilation tutorial covering TorchScript, torch.fx, and Slapo☆17Mar 13, 2023Updated 3 years ago
- A simple baremetal program template for RISC-V inspired from riscv benchmark tests☆11Apr 17, 2018Updated 7 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆65Oct 14, 2025Updated 5 months ago
- ☆43Mar 31, 2025Updated 11 months ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 6 months ago
- The Scala parser to parse riscv/riscv-opcodes generate☆25Jan 21, 2026Updated 2 months ago
- ☆10Sep 7, 2023Updated 2 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆31Jan 29, 2026Updated last month
- ☆12Apr 19, 2022Updated 3 years ago
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated last month
- ☆22Oct 15, 2018Updated 7 years ago
- some sample caffemodel, prototxt, test images and pre compiled loadabes .☆13Apr 30, 2021Updated 4 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Oct 5, 2017Updated 8 years ago
- RISC-V port to Parallella Board☆13Aug 22, 2016Updated 9 years ago
- Nix template for the chisel-based industrial designing flows.☆56Apr 23, 2025Updated 11 months ago
- ☆33Mar 6, 2023Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A Rocket-based RISC-V superscalar in-order core☆38Mar 11, 2026Updated 2 weeks ago
- Basic chisel difftest environment for RTL design (WIP☆20Mar 8, 2025Updated last year
- ☆16Oct 2, 2019Updated 6 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 4 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 9 years ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆19Mar 4, 2026Updated 3 weeks ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆222Jan 23, 2020Updated 6 years ago