Alternatives and similar repositories for somnia

Users that are interested in somnia are comparing it to the libraries listed below

• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆53Updated 5 years ago
• suchandler96 / gem5-NVDLA
  ☆33Updated 4 months ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆22Updated 4 years ago
• plctlab / rvv-benchmark
  PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases
  ☆22Updated 4 years ago
• zeasa / nvdla-compiler
  ☆46Updated 5 years ago
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆28Updated this week
• liang-aquarius / ca_model
  A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…
  ☆15Updated 5 years ago
• sfu-arch / SpGEMM
  ☆36Updated 4 years ago
• pulp-platform / neureka
  2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
  ☆26Updated this week
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆18Updated 6 years ago
• LCAI-TIHU / SW
  LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V
  ☆23Updated 2 years ago
• yonseicasl / NPUsim
  NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators
  ☆39Updated 7 months ago
• pulp-platform / pulp-nn
  ☆83Updated last year
• comparch-security / spike-cache
  Spike with a coherence supported cache model
  ☆13Updated last year
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆80Updated 6 years ago
• WuDan0399 / Integrate-NVDLA-and-TVM
  ☆31Updated 2 years ago
• pulp-platform / redmule
  ☆72Updated 2 weeks ago
• jinhachung / tptpu-sim
  A Toy-Purpose TPU Simulator
  ☆19Updated last year
• tum-ei-eda / mlonmcu
  Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends
  ☆35Updated this week
• ucb-bar / hwacha-template
  Template for projects using the Hwacha data-parallel accelerator
  ☆34Updated 4 years ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 6 months ago
• SCLUO / ITRI-OpenDLA
  OpenDLA for trying the demo and FPGA solution
  ☆17Updated 3 years ago
• shehanmunasinghe / tinyGPU
  tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
  ☆50Updated 4 years ago
• meton-robean / deca
  RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)
  ☆15Updated 5 years ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆39Updated 3 weeks ago
• pulp-platform / pulp-dsp
  ☆34Updated 2 years ago
• THU-DSP-LAB / ventus-gpgpu-isa-simulator
  Ventus GPGPU ISA Simulator Based on Spike
  ☆45Updated last month
• esa-tu-darmstadt / SCAIE-V
  An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:
  ☆16Updated last year
• ucb-bar / virgo
  Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
  ☆36Updated 2 months ago