Alternatives and similar repositories for somnia

Users that are interested in somnia are comparing it to the libraries listed below

• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆53Updated 5 years ago
• suchandler96 / gem5-NVDLA
  ☆31Updated 3 months ago
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆28Updated 3 weeks ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆22Updated 3 years ago
• zeasa / nvdla-compiler
  ☆44Updated 5 years ago
• SameLight / ITRI-OpenDLA
  Express DLA implementation for FPGA, revised based on NVDLA.
  ☆9Updated 5 years ago
• yonseicasl / NPUsim
  NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators
  ☆36Updated 6 months ago
• pulp-platform / dram_rtl_sim
  ☆15Updated last week
• WuDan0399 / Integrate-NVDLA-and-TVM
  ☆31Updated 2 years ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆37Updated 3 weeks ago
• plctlab / rvv-benchmark
  PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases
  ☆22Updated 4 years ago
• SCLUO / ITRI-OpenDLA
  OpenDLA for trying the demo and FPGA solution
  ☆16Updated 2 years ago
• liang-aquarius / ca_model
  A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…
  ☆15Updated 5 years ago
• sfu-arch / SpGEMM
  ☆36Updated 4 years ago
• comparch-security / spike-cache
  Spike with a coherence supported cache model
  ☆13Updated last year
• pulp-platform / pulp-nn
  ☆82Updated last year
• pulp-platform / neureka
  2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
  ☆26Updated 3 weeks ago
• meton-robean / deca
  RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)
  ☆15Updated 5 years ago
• prasshantg / personal
  ☆17Updated 5 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• pulp-platform / redmule
  ☆68Updated last week
• ucb-bar / virgo
  Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
  ☆35Updated last month
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 4 months ago
• amin-norollah / PAT-Noxim
  cycle accurate Network-on-Chip Simulator
  ☆28Updated 2 years ago
• THU-DSP-LAB / ventus-gpgpu-isa-simulator
  Ventus GPGPU ISA Simulator Based on Spike
  ☆43Updated this week
• GramThanos / CPU-on-Vivado-HLS
  A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS
  ☆18Updated 5 years ago
• jinhachung / tptpu-sim
  A Toy-Purpose TPU Simulator
  ☆19Updated last year
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆17Updated 5 years ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆80Updated 6 years ago
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 2 years ago