A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.
☆15Jan 14, 2022Updated 4 years ago
Alternatives and similar repositories for falco
Users that are interested in falco are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Aquila: a 32-bit RISC-V processor for Xilinx FPGAs.☆38Oct 25, 2023Updated 2 years ago
- A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines☆11Nov 28, 2019Updated 6 years ago
- a hardware task scheduler design☆10Sep 14, 2022Updated 4 years ago
- Hardware Description Language on FPGA☆12Sep 18, 2023Updated 3 years ago
- a verilog snake game program☆11Oct 13, 2022Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Designing a Multi-Agent Fabric Integration Architecture to run on de10-lite FPGA.☆19Apr 28, 2026Updated 4 months ago
- 陽明交通大學/台灣大學 修課心得😀☆21Jul 7, 2024Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- ☆20Dec 21, 2020Updated 5 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆21Sep 5, 2021Updated 5 years ago
- Reconfigurable Binary Engine☆18Mar 23, 2021Updated 5 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆20Updated this week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆191Apr 4, 2026Updated 5 months ago
- Designing Video Game Hardware in Verilog☆29Jan 5, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆34Jun 30, 2021Updated 5 years ago
- DUTH RISC-V Microprocessor☆26Apr 5, 2026Updated 5 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆239Aug 25, 2020Updated 6 years ago
- ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor☆11Aug 23, 2017Updated 9 years ago
- ☆10May 12, 2022Updated 4 years ago
- ☆59Jul 2, 2023Updated 3 years ago
- ☆33Nov 25, 2022Updated 3 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- Repo for PyChart 1.39, refs http://download.gna.org/pychart/☆10Sep 29, 2014Updated 11 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Sparse-dense matrix-matrix multiplication on GPUs☆13Oct 15, 2018Updated 7 years ago
- ☆10Apr 8, 2021Updated 5 years ago
- This repo is for Edge Vision SoC framework, which facilitates quick porting of users' design for Edge AI and Vision solutions.☆35Jul 1, 2026Updated 2 months ago
- Wraps the NVDLA project for Chipyard integration☆24Sep 2, 2025Updated last year
- OpenTitan: Open source silicon root of trust☆10Feb 5, 2020Updated 6 years ago
- Hardware Implementation of low-bit rate Codec, Codec2 in Verilog RTL on Cyclone IV FPGA.☆15Mar 29, 2020Updated 6 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- The MiBench testsuite, extended for use in general embedded environments☆15Oct 20, 2018Updated 7 years ago
- A Kubernetes cluster to learn Kubernetes. It includes Argo CD, Grafana, Prometheus, Loki, Tempo, Phlare and VictoriaMetrics.☆11Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- PSO , Simulated Annealing PSO , Chaotic SAPSO, Neural network, Nonlinear Function☆12Apr 6, 2022Updated 4 years ago
- LinkIt Connect 7681 AT command support☆12Jan 27, 2016Updated 10 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- An example model of a Network Processing Unit using the PFPSim framework.☆13Aug 23, 2016Updated 10 years ago
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆40Mar 27, 2018Updated 8 years ago
- Sniffer,大二网络编程的课程设计☆10Feb 28, 2022Updated 4 years ago
- Branch Predictor Optimization for BlackParrot☆15Mar 24, 2024Updated 2 years ago