eisl-nctu / falco
A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.
☆16Updated 3 years ago
Alternatives and similar repositories for falco:
Users that are interested in falco are comparing it to the libraries listed below
- DUTH RISC-V Superscalar Microprocessor☆29Updated 2 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆32Updated 4 years ago
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Updated last year
- Reconfigurable Binary Engine☆15Updated 3 years ago
- Neural Network accelerator powered by MVUs and RISC-V.☆12Updated 5 months ago
- DUTH RISC-V Microprocessor☆19Updated last month
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆20Updated 4 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated last month
- ☆25Updated 4 years ago
- ☆24Updated 5 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆25Updated 3 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 2 years ago
- PCI Express controller model☆47Updated 2 years ago
- ☆12Updated 2 years ago
- HLS for Networks-on-Chip☆32Updated 3 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆12Updated 8 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆33Updated 2 years ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆4Updated 2 years ago
- YSYX RISC-V Project NJU Study Group☆13Updated 2 weeks ago
- Platform Level Interrupt Controller☆35Updated 8 months ago
- RISC-V soft-core PEs for TaPaSCo☆17Updated 7 months ago
- SystemC training aimed at TLM.☆27Updated 4 years ago
- ☆40Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆62Updated 4 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆17Updated 11 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆30Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆47Updated 3 years ago
- General Purpose AXI Direct Memory Access☆48Updated 8 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 9 months ago
- ☆21Updated last week