hankshyu / RISC-V_MACLinks
MAC system with IEEE754 compatibility
☆13Updated last year
Alternatives and similar repositories for RISC-V_MAC
Users that are interested in RISC-V_MAC are comparing it to the libraries listed below
Sorting:
- a hardware task scheduler design☆9Updated 2 years ago
- ☆14Updated 2 years ago
- ☆27Updated 5 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆12Updated 2 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆10Updated 6 years ago
- Template for project1 TPU☆19Updated 4 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- a verilog snake game program☆10Updated 2 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 3 years ago
- DMA controller for CNN accelerator☆13Updated 8 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated 4 months ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆12Updated 2 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- A scalable Eyeriss model in SystemC.☆28Updated 2 years ago
- EE577b-Course-Project☆17Updated 5 years ago
- Neural Network accelerator powered by MVUs and RISC-V.☆13Updated 11 months ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆13Updated 6 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆14Updated last year
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆29Updated last year
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- Development of a Network on Chip Simulation using SystemC.☆33Updated 7 years ago
- ☆14Updated 2 years ago
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆22Updated last year
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 3 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 6 years ago