hankshyu / RISC-V_MAC
MAC system with IEEE754 compatibility
☆10Updated last year
Alternatives and similar repositories for RISC-V_MAC:
Users that are interested in RISC-V_MAC are comparing it to the libraries listed below
- a hardware task scheduler design☆9Updated 2 years ago
- ☆12Updated 2 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆13Updated 11 months ago
- Design and UVM-TB of RISC -V Microprocessor☆14Updated 6 months ago
- CNN accelerator using NoC architecture☆15Updated 6 years ago
- CORDIC VLSI-IP for deep learning activation functions☆13Updated 5 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆12Updated 6 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆9Updated last year
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆9Updated last year
- This repo is "NTHU VLSI System Design and Implementation" course project.☆11Updated 7 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Updated 10 years ago
- A scalable Eyeriss model in SystemC.☆24Updated 2 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆10Updated 5 years ago
- NCTU 2018 Spring Integrated Circuit Design Laboratory☆24Updated 6 years ago
- The template for VLSI project☆17Updated 5 years ago
- RTL code of some arbitration algorithm☆13Updated 5 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆14Updated 5 months ago
- NoC based MPSoC☆10Updated 10 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆10Updated 4 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆18Updated 7 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- EE577b-Course-Project☆16Updated 4 years ago
- To design test bench of the APB protocol☆16Updated 4 years ago
- DMA controller for CNN accelerator☆13Updated 7 years ago
- ☆17Updated 9 years ago
- ☆11Updated 10 months ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Updated 5 years ago
- Neural Network accelerator powered by MVUs and RISC-V.☆12Updated 6 months ago
- ☆24Updated 5 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆17Updated 11 years ago