A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz.
☆17Jan 4, 2020Updated 6 years ago
Alternatives and similar repositories for trivial-riscv-cpu
Users that are interested in trivial-riscv-cpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Some learning materials, notes and scripts about the programming and security of microcontroller.☆15Mar 15, 2022Updated 4 years ago
- A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines☆11Nov 28, 2019Updated 6 years ago
- A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.☆15Jan 14, 2022Updated 4 years ago
- [USENIX Security 25] PatchAgent is a LLM-based practical program repair agent that mimics human expertise.☆120Feb 25, 2026Updated last month
- CAMP: Compiler and Allocator-based Heap Memory Protection (USENIX Security 2024) ✨☆46Jul 18, 2024Updated last year
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Log file scanner used with EDA tools to classify errors and warnings☆12Nov 14, 2022Updated 3 years ago
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆41Mar 27, 2018Updated 8 years ago
- Formal Verification of RISC V IM Processor☆11Mar 27, 2022Updated 4 years ago
- my rc files☆12Mar 16, 2016Updated 10 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Jul 13, 2019Updated 6 years ago
- Bluespec H.264 Decoder☆12Jul 17, 2014Updated 11 years ago
- ☆12Aug 12, 2022Updated 3 years ago
- Computer architecture learning environment using FPGAs☆15May 17, 2021Updated 4 years ago
- ☆14Jul 28, 2022Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- 合肥工业大学《系统硬件综合设计》五级流水线 RISC-V CPU☆33Sep 24, 2023Updated 2 years ago
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Jun 7, 2015Updated 10 years ago
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 8 years ago
- Deep SNNs with various neural coding methods (rate, phase, burst, TTFS)☆12Feb 15, 2022Updated 4 years ago
- VCD file viewer for Neovim☆15Feb 20, 2022Updated 4 years ago
- Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"☆11Apr 20, 2023Updated 2 years ago
- Verilator open-source SystemVerilog simulator and lint system☆23Apr 10, 2026Updated last week
- 32-bit soft RISCV processor for FPGA applications☆19Nov 25, 2023Updated 2 years ago
- A CORDIC implementation of square root Verilog calculation on Quartus Prime 16.0, with ability to simulate on ModelSim as well.☆19Jul 24, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Spiking Neural Network Accelerator☆15May 18, 2022Updated 3 years ago
- Repo for PyChart 1.39, refs http://download.gna.org/pychart/☆10Sep 29, 2014Updated 11 years ago
- RISC-V instruction set extensions for SM4 block cipher☆21Mar 6, 2020Updated 6 years ago
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 11 years ago
- Heterogeneous Programming☆18Apr 24, 2023Updated 2 years ago
- all kind of notes, I maybe sort this in the future☆13Aug 29, 2025Updated 7 months ago
- A small Neural Network Processor for Edge devices.☆18Nov 22, 2022Updated 3 years ago
- Hardware and software implementation of Sparsely-active SNNs☆22Mar 6, 2026Updated last month
- ☆23Apr 11, 2026Updated last week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- A Homework for Computer Architecture at SJTU☆14Jan 4, 2020Updated 6 years ago
- 重庆大学计算机学院2018级计算机体系结构cache设计☆11Jan 4, 2021Updated 5 years ago
- RISC-V System on Chip Builder☆12Sep 27, 2020Updated 5 years ago
- ☆10Updated this week
- An example model of a Network Processing Unit using the PFPSim framework.☆13Aug 23, 2016Updated 9 years ago
- SJTU Computer Architecture(1) Hw☆14Jan 12, 2018Updated 8 years ago
- ☆14Nov 20, 2019Updated 6 years ago