A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz.
☆16Jan 4, 2020Updated 6 years ago
Alternatives and similar repositories for trivial-riscv-cpu
Users that are interested in trivial-riscv-cpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines☆11Nov 28, 2019Updated 6 years ago
- A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.☆15Jan 14, 2022Updated 4 years ago
- Log file scanner used with EDA tools to classify errors and warnings☆13Nov 14, 2022Updated 3 years ago
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆41Mar 27, 2018Updated 8 years ago
- Formal Verification of RISC V IM Processor☆11Mar 27, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- An FPGA-based RISC-V CPU☆16Dec 7, 2021Updated 4 years ago
- my rc files☆12Mar 16, 2016Updated 10 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Jul 13, 2019Updated 6 years ago
- Bluespec H.264 Decoder☆12Jul 17, 2014Updated 11 years ago
- ☆12Aug 12, 2022Updated 3 years ago
- Computer architecture learning environment using FPGAs☆15May 17, 2021Updated 4 years ago
- 合肥工业大学《系统硬件综合设计》五级流水线 RISC-V CPU☆33Sep 24, 2023Updated 2 years ago
- This repo is for the Linkedin Learning course: Training Neural Networks in C++☆12Oct 24, 2023Updated 2 years ago
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Jun 7, 2015Updated 10 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 8 years ago
- Deep SNNs with various neural coding methods (rate, phase, burst, TTFS)☆12Feb 15, 2022Updated 4 years ago
- Companion Material for the book: Building Embedded Systems - Programmable Hardware☆14Jun 6, 2016Updated 9 years ago
- VCD file viewer for Neovim☆15Feb 20, 2022Updated 4 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆49Jul 4, 2019Updated 6 years ago
- Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"☆11Apr 20, 2023Updated 3 years ago
- Advanced Programming for Computer Design Problems☆17Aug 28, 2021Updated 4 years ago
- Verilator open-source SystemVerilog simulator and lint system☆23Apr 30, 2026Updated last week
- Create and use hybrid workflows to solve problems.☆12Oct 31, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A CORDIC implementation of square root Verilog calculation on Quartus Prime 16.0, with ability to simulate on ModelSim as well.☆19Jul 24, 2021Updated 4 years ago
- Repo for PyChart 1.39, refs http://download.gna.org/pychart/☆10Sep 29, 2014Updated 11 years ago
- RISC-V instruction set extensions for SM4 block cipher☆21Mar 6, 2020Updated 6 years ago
- Region-level profiling for CUDA kernels with trace, NVBit, CUPTI, NSys, and an interactive Explorer.☆115Apr 17, 2026Updated 3 weeks ago
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 11 years ago
- 关于深度学习算法、框架、编译器、加速器的一些理解☆16Jul 2, 2022Updated 3 years ago
- all kind of notes, I maybe sort this in the future☆13Aug 29, 2025Updated 8 months ago
- Hardware and software implementation of Sparsely-active SNNs☆22Mar 6, 2026Updated 2 months ago
- A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL☆96Dec 5, 2019Updated 6 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A Homework for Computer Architecture at SJTU☆14Jan 4, 2020Updated 6 years ago
- Scripts to recover (accidentally) deleted files from ext3 partitions☆14Aug 16, 2017Updated 8 years ago
- A small Neural Network Processor for Edge devices.☆19Nov 22, 2022Updated 3 years ago
- RISC-V System on Chip Builder☆12Sep 27, 2020Updated 5 years ago
- An example model of a Network Processing Unit using the PFPSim framework.☆13Aug 23, 2016Updated 9 years ago
- SJTU Computer Architecture(1) Hw☆14Jan 12, 2018Updated 8 years ago
- 计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab11~12 & 14~15☆22Dec 22, 2020Updated 5 years ago