EECS150 / fpga_labs_fa21Links
FPGA Labs for EECS 151/251A (Fall 2021)
☆10Updated 4 years ago
Alternatives and similar repositories for fpga_labs_fa21
Users that are interested in fpga_labs_fa21 are comparing it to the libraries listed below
Sorting:
- The official NaplesPU hardware code repository☆20Updated 6 years ago
- DUTH RISC-V Superscalar Microprocessor☆32Updated last year
- ☆31Updated 5 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆21Updated 7 months ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆31Updated 4 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆25Updated 3 months ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆20Updated last week
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- ☆32Updated 3 weeks ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11Updated 6 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- RISC-V soft-core PEs for TaPaSCo☆23Updated last year
- ☆69Updated 4 years ago
- To design test bench of the APB protocol☆18Updated 4 years ago
- Generic AXI master stub☆19Updated 11 years ago
- ☆33Updated 3 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated last year
- Two Level Cache Controller implementation in Verilog HDL☆53Updated 5 years ago
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆27Updated last month
- ☆13Updated 7 months ago
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- A Verilog implementation of a processor cache.☆34Updated 7 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆67Updated 9 years ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- A repository for SystemC Learning examples☆72Updated 3 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- Design and UVM-TB of RISC -V Microprocessor☆32Updated last year