Alternatives and similar repositories for rioschip:

Users that are interested in rioschip are comparing it to the libraries listed below

• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆45Updated 8 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• AL-255 / Project-Yatsuhashi-Chip1
  ☆39Updated 2 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• pulp-platform / axi_llc
  ☆23Updated 3 weeks ago
• aignacio / nox
  RISC-V Nox core
  ☆62Updated 7 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆40Updated last year
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆48Updated 2 years ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆29Updated 4 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆14Updated 2 months ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆36Updated last week
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆37Updated 10 months ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated this week
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆30Updated 5 months ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆41Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 6 months ago
• Open-Source-Hardware-Initiative / AES
  Open Source AES
  ☆31Updated 11 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆32Updated this week
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆46Updated 4 months ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆30Updated 3 years ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 8 months ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• google / globalfoundries-pdks
  Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.
  ☆48Updated 2 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆40Updated 3 months ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆31Updated last month
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆23Updated 5 years ago