ecilasun / NekoIchiLinks
A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board
☆31Updated 4 years ago
Alternatives and similar repositories for NekoIchi
Users that are interested in NekoIchi are comparing it to the libraries listed below
Sorting:
- A SoC for DOOM☆19Updated 4 years ago
- ☆33Updated 3 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- 3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.☆90Updated 5 years ago
- FPGA GPU design for DE1-SoC☆73Updated 3 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆108Updated 3 weeks ago
- A Risc-V SoC for Tiny Tapeout☆43Updated this week
- IEEE 754 single precision floating point library in systemverilog and vhdl☆38Updated 11 months ago
- SoftCPU/SoC engine-V☆55Updated 8 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆54Updated 2 years ago
- ☆60Updated 4 years ago
- RISCV CPU implementation in SystemVerilog☆32Updated 2 months ago
- LunaPnR is a place and router for integrated circuits☆47Updated 4 months ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆20Updated last week
- RISC-V Nox core☆69Updated 4 months ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 4 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆30Updated 12 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- ☆17Updated 5 years ago
- PicoRV☆43Updated 5 years ago
- USB virtual model in C++ for Verilog☆32Updated last year
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆70Updated 3 years ago
- RISC-V processor☆32Updated 3 years ago
- ☆38Updated 3 years ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Minimal DVI / HDMI Framebuffer☆82Updated 5 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆73Updated last week
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated last year
- Wishbone interconnect utilities☆43Updated 9 months ago