A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board
☆33Jun 30, 2021Updated 4 years ago
Alternatives and similar repositories for NekoIchi
Users that are interested in NekoIchi are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆33Nov 25, 2022Updated 3 years ago
- FPGA GPU design for DE1-SoC☆73Dec 27, 2021Updated 4 years ago
- Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.☆18Feb 26, 2023Updated 3 years ago
- 3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.☆91Oct 3, 2020Updated 5 years ago
- Typhoon GPU on FPGA☆12Aug 22, 2019Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- Isle FPGA Computer☆75Mar 20, 2026Updated last week
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 5 years ago
- QQSPI Pmod-compatible 32MB PSRAM module☆16Sep 14, 2023Updated 2 years ago
- Latest in the line of the E32 processors with better/generic cache placement☆10Feb 25, 2023Updated 3 years ago
- Programmable multichannel ADPCM decoder for FPGA☆25Dec 28, 2020Updated 5 years ago
- A very simple SDRAM controller for FPGA written in Verilog. It exposes a SRAM-like interface to the rest of the FPGA fabric☆14Dec 4, 2018Updated 7 years ago
- Simple Path Tracer on an FPGA☆34Aug 29, 2021Updated 4 years ago
- A SoC for DOOM☆20Apr 11, 2021Updated 4 years ago
- OpenGL 1.x implementation for FPGAs☆115Mar 15, 2026Updated last week
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- The binaries for SaxonSoc Linux and other configurations☆17Mar 23, 2023Updated 3 years ago
- ☆15May 17, 2025Updated 10 months ago
- A VHDL code generator for wallace tree multiplier☆10Apr 15, 2020Updated 5 years ago
- Introduction to FPGA emulation and digital design. This capstone project was part of the 2021 University of San Diego Shiley-Marcos Schoo…☆55Mar 22, 2022Updated 4 years ago
- ☆18Dec 6, 2020Updated 5 years ago
- Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).☆62Mar 5, 2023Updated 3 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Jun 12, 2023Updated 2 years ago
- SystemVerilog modules and classes commonly used for verification☆57Jan 5, 2026Updated 2 months ago
- Designing a Multi-Agent Fabric Integration Architecture to run on de10-lite FPGA.☆17Feb 2, 2026Updated last month
- NordVPN Threat Protection Pro™ • AdTake your cybersecurity to the next level. Block phishing, malware, trackers, and ads. Lightweight app that works with all browsers.
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆37Mar 19, 2026Updated last week
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice☆37Jul 2, 2023Updated 2 years ago
- Simple BLE demo using an iOS app (SwiftUI), an ESP32 (Python) and an FPGA (Verilog)☆16Dec 12, 2020Updated 5 years ago
- A RISC-V processor☆15Dec 11, 2018Updated 7 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Jun 28, 2025Updated 9 months ago
- Technology file parser in Rust☆13Apr 6, 2021Updated 4 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Feb 23, 2026Updated last month
- Matra-Hachette Alice MC-10 for MiSTer FPGA☆12Dec 8, 2025Updated 3 months ago
- Memory-mapped VGA display for Xilinx/Zynq/Zedboard, with demo code for using it.☆15Feb 26, 2018Updated 8 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- AXI memory-mapped VGA module originally designed for the Avent Zedboard☆16Aug 2, 2016Updated 9 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Sep 24, 2020Updated 5 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆21Sep 5, 2021Updated 4 years ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆26Jan 1, 2022Updated 4 years ago
- A collection of SPI related cores☆21Nov 12, 2024Updated last year
- A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.☆15Jan 14, 2022Updated 4 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆18Feb 27, 2025Updated last year