ecilasun / NekoIchi
A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board
☆28Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for NekoIchi
- ☆32Updated last year
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆40Updated 11 months ago
- A pipelined RISC-V processor☆47Updated 11 months ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆26Updated 3 weeks ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- 3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.☆70Updated 4 years ago
- LunaPnR is a place and router for integrated circuits☆43Updated 3 months ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆48Updated last year
- A Risc-V SoC for Tiny Tapeout☆10Updated last week
- SoftCPU/SoC engine-V☆54Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆62Updated this week
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- Wishbone interconnect utilities☆36Updated 5 months ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆29Updated 4 months ago
- A RISC-V processor☆13Updated 5 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆18Updated 3 weeks ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆41Updated 2 weeks ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆64Updated 2 years ago
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆36Updated 6 months ago
- Minimal DVI / HDMI Framebuffer☆74Updated 4 years ago
- ☆57Updated 3 years ago
- Dual-issue RV64IM processor for fun & learning☆57Updated last year
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆72Updated 2 months ago
- A SoC for DOOM☆16Updated 3 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆44Updated this week
- ☆36Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆60Updated 7 months ago
- Latest in the line of the E32 processors with better/generic cache placement☆10Updated last year
- Naive Educational RISC V processor☆71Updated 3 weeks ago