☆15Jul 28, 2022Updated 4 years ago
Alternatives and similar repositories for lpddr4_memory_controller
Users that are interested in lpddr4_memory_controller are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆33Feb 20, 2024Updated 2 years ago
- SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge☆15Sep 9, 2022Updated 4 years ago
- An Open Source Link Protocol and Controller☆29Aug 1, 2021Updated 5 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆98Feb 28, 2018Updated 8 years ago
- Experimental breakout board for a signle 200-ball WFBGA LPDDR4 chip in SO-DIMM DDR4 form factor.☆27Dec 11, 2025Updated 10 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Papers, Posters, Presentations, Documentation...☆20Jan 9, 2024Updated 2 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆45Updated this week
- ☆17Nov 11, 2015Updated 10 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated 2 years ago
- ☆12May 29, 2020Updated 6 years ago
- ☆10Dec 15, 2023Updated 2 years ago
- Implementations of the XNOR networks☆12Aug 9, 2017Updated 9 years ago
- RISC-V IOMMU in verilog☆22Jun 18, 2022Updated 4 years ago
- Verification IP for APB protocol☆34Sep 9, 2020Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- There are many RISC V projects on iCE40. This one is mine.☆16Jun 25, 2020Updated 6 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆40Nov 24, 2022Updated 3 years ago
- AIA IP compliant with the RISC-V AIA spec☆47Sep 7, 2026Updated last month
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆159Mar 19, 2018Updated 8 years ago
- Small footprint and configurable DRAM core☆563Updated this week
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 4 years ago
- Formal Verification of RISC V IM Processor☆12Mar 27, 2022Updated 4 years ago
- EE P 520 A Wi 20: Software Engineering For Embedded Applications☆11Mar 13, 2020Updated 6 years ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆25Mar 7, 2019Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- This is a convert tool to create AIfES models for direct use in the Arduino IDE or other IDEs.☆15Sep 20, 2022Updated 4 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 7 years ago
- ☆21Jan 13, 2026Updated 9 months ago
- my rc files☆12Mar 16, 2016Updated 10 years ago
- RTL code of some arbitration algorithm☆16Aug 25, 2019Updated 7 years ago
- ☆20Dec 21, 2020Updated 5 years ago
- IOPMP IP☆26Jul 11, 2025Updated last year
- This is a brand new implement of GPGPU called Koala GPU which will be compatible with NV GPU micro architecture starting from fermi. It s…☆19May 31, 2026Updated 4 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- QSPI for SoC☆24Nov 8, 2019Updated 6 years ago
- ☆13Jul 5, 2026Updated 3 months ago
- Improved version of http://web.mit.edu/6.111/volume2/www/f2018/tools/sd_controller.v☆13Dec 6, 2021Updated 4 years ago
- ☆22Sep 26, 2025Updated last year
- Simple Verilog Parser In Python☆15Dec 31, 2017Updated 8 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆20Sep 25, 2026Updated 2 weeks ago
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆21Oct 5, 2026Updated last week