☆14Jul 28, 2022Updated 3 years ago
Alternatives and similar repositories for lpddr4_memory_controller
Users that are interested in lpddr4_memory_controller are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge☆13Sep 9, 2022Updated 3 years ago
- An Open Source Link Protocol and Controller☆28Aug 1, 2021Updated 4 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆126Jul 22, 2021Updated 4 years ago
- Papers, Posters, Presentations, Documentation...☆19Jan 9, 2024Updated 2 years ago
- ☆13Nov 11, 2015Updated 10 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆17Jul 3, 2025Updated 9 months ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆23Apr 25, 2025Updated 11 months ago
- ☆29Feb 20, 2024Updated 2 years ago
- ☆10Dec 15, 2023Updated 2 years ago
- ☆21Sep 26, 2025Updated 6 months ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆93Feb 28, 2018Updated 8 years ago
- ☆22May 13, 2025Updated 11 months ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 3 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆147Mar 19, 2018Updated 8 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆25Updated this week
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Feb 23, 2026Updated last month
- EE P 520 A Wi 20: Software Engineering For Embedded Applications☆11Mar 13, 2020Updated 6 years ago
- ☆17Dec 21, 2020Updated 5 years ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆24Mar 7, 2019Updated 7 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- Deploy open-source AI quickly and easily - Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆22Mar 25, 2025Updated last year
- my rc files☆12Mar 16, 2016Updated 10 years ago
- Formal Verification of RISC V IM Processor☆10Mar 27, 2022Updated 4 years ago
- Verilog Ethernet Switch (layer 2)☆57Oct 18, 2023Updated 2 years ago
- RTL code of some arbitration algorithm☆16Aug 25, 2019Updated 6 years ago
- QSPI for SoC☆23Nov 8, 2019Updated 6 years ago
- ☆14Mar 13, 2026Updated last month
- Verilog PCI express components☆25Jun 26, 2023Updated 2 years ago
- Small footprint and configurable DRAM core☆492Updated this week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆18Feb 27, 2025Updated last year
- Simple Verilog Parser In Python☆15Dec 31, 2017Updated 8 years ago
- Experimental breakout board for a signle 200-ball WFBGA LPDDR4 chip in SO-DIMM DDR4 form factor.☆20Dec 11, 2025Updated 4 months ago
- The official NaplesPU hardware code repository☆24Jul 27, 2019Updated 6 years ago
- Region-level profiling for CUDA kernels with trace, NVBit, CUPTI, and an interactive Explorer.☆103Mar 27, 2026Updated 2 weeks ago
- Documentation for the entire CGRAFlow☆19Sep 17, 2021Updated 4 years ago
- Network on Chip for MPSoC☆28Updated this week