amichai-bd / riscv-multi-core-lotrLinks
RISCV core RV32I/E.4 threads in a ring architecture
☆32Updated 2 years ago
Alternatives and similar repositories for riscv-multi-core-lotr
Users that are interested in riscv-multi-core-lotr are comparing it to the libraries listed below
Sorting:
- ☆29Updated 3 weeks ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆46Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 10 months ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 months ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 7 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆35Updated 8 months ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆22Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆43Updated 5 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆29Updated 2 months ago
- Platform Level Interrupt Controller☆42Updated last year
- ☆33Updated 2 years ago
- ☆32Updated this week
- Verilog HDL implementation of SDRAM controller and SDRAM model☆29Updated last year
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- ☆19Updated last week
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- ☆40Updated last year
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated 2 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated last week
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 9 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆19Updated 4 years ago
- ☆61Updated 4 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆30Updated 3 months ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- Open Source PHY v2☆30Updated last year