amichai-bd / riscv-multi-core-lotr

Related projects ⓘ

Alternatives and complementary repositories for riscv-multi-core-lotr

• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆35Updated 6 months ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆28Updated last month
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆30Updated 3 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆26Updated 9 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆22Updated last month
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆29Updated 3 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆43Updated 2 years ago
• pulp-platform / axi_llc
  ☆21Updated 2 months ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆59Updated 3 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆67Updated 6 months ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 2 years ago
• aignacio / mpsoc_example
  ☆57Updated 3 years ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆35Updated 2 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 4 months ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆56Updated 2 weeks ago
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆38Updated 5 months ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆40Updated this week
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆17Updated 5 months ago
• IObundle / iob-lib
  Verilog Modules and Python Scripts for Creating IP Core Build Directories
  ☆29Updated last year
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆33Updated last year
• pulp-platform / rbe
  Reconfigurable Binary Engine
  ☆15Updated 3 years ago
• AlSaqr-platform / he-soc
  ☆33Updated this week
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆26Updated last month
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆25Updated 4 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 4 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆63Updated 7 months ago
• pulp-platform / fpu
  ☆37Updated 5 years ago
• verilator / example-systemverilog
  ☆34Updated 10 months ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆17Updated last year