amichai-bd / riscv-multi-core-lotrLinks
RISCV core RV32I/E.4 threads in a ring architecture
☆33Updated 2 years ago
Alternatives and similar repositories for riscv-multi-core-lotr
Users that are interested in riscv-multi-core-lotr are comparing it to the libraries listed below
Sorting:
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆32Updated last year
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- The RTL source for AnyCore RISC-V☆33Updated 3 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- ☆32Updated last week
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated 2 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated 11 months ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆18Updated 7 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 10 months ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 9 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated last month
- ☆32Updated last month
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆40Updated last week
- FPGA reference design for the the Swerv EH1 Core☆72Updated 5 years ago
- ☆60Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 4 months ago
- ☆13Updated 6 months ago
- DDR4 Simulation Project in System Verilog☆42Updated 11 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- ☆20Updated last month
- The official NaplesPU hardware code repository☆20Updated 6 years ago
- ASIC Design of the openSPARC Floating Point Unit☆15Updated 8 years ago