Alternatives and similar repositories for riscv-multi-core-lotr

Users that are interested in riscv-multi-core-lotr are comparing it to the libraries listed below

• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆45Updated 3 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 9 months ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆32Updated 3 years ago
• pulp-platform / axi_llc
  ☆30Updated last week
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆34Updated 7 months ago
• merledu / azadi-soc
  Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
  ☆32Updated last year
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆35Updated 4 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 5 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated last month
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 4 years ago
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆24Updated 6 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆33Updated 6 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆50Updated 9 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆35Updated this week
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆22Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆31Updated 8 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆66Updated 5 months ago
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆28Updated last month
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆28Updated 9 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆30Updated 2 months ago
• yigitbektasgursoy / SDRAM_Verilog
  Verilog HDL implementation of SDRAM controller and SDRAM model
  ☆27Updated last year
• aignacio / nox
  RISC-V Nox core
  ☆66Updated last week
• martinriis / RISC-V-Vector-Processor
  256-bit vector processor based on the RISC-V vector (V) extension
  ☆30Updated 4 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆63Updated 6 months ago
• pulp-platform / uvm-components
  Contains commonly used UVM components (agents, environments and tests).
  ☆29Updated 6 years ago