efabless / foss-asic-toolsLinks
FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already installed and ready to use.
☆102Updated last year
Alternatives and similar repositories for foss-asic-tools
Users that are interested in foss-asic-tools are comparing it to the libraries listed below
Sorting:
- JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.☆74Updated 6 months ago
- ☆84Updated 2 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆192Updated last month
- Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs☆74Updated 2 months ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆65Updated last month
- ☆83Updated 9 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆74Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆79Updated 4 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- ☆178Updated 4 years ago
- ☆118Updated 2 years ago
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆167Updated 2 months ago
- repository for a bandgap voltage reference in SKY130 technology☆40Updated 2 years ago
- Course material for a basic hands-on analog circuit design course with IC emphasis☆152Updated this week
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆43Updated 3 years ago
- ☆43Updated 3 years ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆295Updated this week
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 3 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆162Updated 2 years ago
- A tiny Python package to parse spice raw data files.☆53Updated 2 years ago
- Home of the open-source EDA course.☆46Updated 4 months ago
- Verilog-A simulation models☆84Updated 2 months ago
- Python script for generating lookup tables for the gm/ID design methodology and much more ...☆102Updated 6 months ago
- ☆106Updated 2 weeks ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆76Updated 2 years ago
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- A complete open-source design-for-testing (DFT) Solution☆164Updated last month
- Circuit Automatic Characterization Engine☆50Updated 8 months ago
- SystemVerilog RTL Linter for YoSys☆21Updated 11 months ago