Integrated Circuit Design - IC Design Flow and Project-Based Learning
☆60Mar 1, 2026Updated 7 months ago
Alternatives and similar repositories for IC-Design
Users that are interested in IC-Design are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.☆24Updated this week
- Resources for my first book☆22Jun 21, 2023Updated 3 years ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆37Mar 23, 2024Updated 2 years ago
- "The Drop" ASIC 640x480 60Hz audio visual demo☆14Feb 11, 2026Updated 7 months ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆20Jan 27, 2023Updated 3 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- 🚀 Real-Time High-Level Synthesis (HLS) Projects for UltraScale+ FPGAs. Accelerated design pipelines, dataflow architectures, and low-lat…☆16Aug 2, 2026Updated 2 months ago
- The code about TC-Bench and CircuitMind☆19Jun 7, 2025Updated last year
- Open-source 8×8 INT8 systolic array inference accelerator — from RTL to bitstream☆25Aug 2, 2026Updated 2 months ago
- Submission template for Tiny Tapeout 9 - Verilog HDL Projects☆15Nov 13, 2024Updated last year
- ☆27May 31, 2021Updated 5 years ago
- ASIC implementation flow infrastructure, successor to OpenLane☆577Updated this week
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- This repository contains my work from the VLSI System Design (VSD) Workshop on 7nm FinFET Circuit Design and Characterization using the A…☆16Sep 9, 2025Updated last year
- [Course] Hands-On ZYNQ: Mastering AXI4 Bus Protocol☆19Feb 22, 2020Updated 6 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Vitis-AI 1.3 TensorFlow2 flow with a custom CNN model, targeted ZCU102 evaluation board.☆15Apr 6, 2021Updated 5 years ago
- ☆10Jun 26, 2025Updated last year
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆19Mar 30, 2025Updated last year
- SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations☆22Apr 12, 2026Updated 5 months ago
- A Reconfigurable RISC-V Core for Approximate Computing☆132May 30, 2025Updated last year
- 🏆 Amazon Best Seller | Full-stack AI NPU Design (Python, Verilog, ISA, FPGA) Vol.2 Coming Soon!☆30Mar 3, 2026Updated 7 months ago
- An open source, parameterized SystemVerilog digital hardware IP library☆33May 26, 2024Updated 2 years ago
- A portable parser combinator library that does not require a runtime☆13Sep 16, 2019Updated 7 years ago
- ARCH hardware description language and compiler☆78Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This is a complementary extension to the https://hub.docker.com/r/hpretl/iic-osic-tools Docker image, adding support for RF simulations a…☆17Aug 18, 2026Updated last month
- Simple command line to get directory information☆14Jul 25, 2026Updated 2 months ago
- Signal processing features based on xtensor☆12Nov 25, 2023Updated 2 years ago
- UART in Verilog and VHDL☆18Aug 21, 2022Updated 4 years ago
- Bilingual FPGA-based SDR course for Zynq with labs, hardware workflow, MATLAB/Simulink and DSP implementation track☆98Updated this week
- Port of ciccreator to Python☆23Sep 29, 2026Updated last week
- An example repo for generating python bindings with cppyy.☆14Nov 19, 2019Updated 6 years ago
- An Oberon-07 Compiler for the ESP32 Processor☆10Jan 4, 2021Updated 5 years ago
- Accelerator Zoo☆21Oct 14, 2025Updated 11 months ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆18Sep 12, 2023Updated 3 years ago
- 💎 A 32-bit ARM Processor Implementation in Verilog HDL☆30Mar 21, 2022Updated 4 years ago
- ☆218Apr 26, 2026Updated 5 months ago
- FPGA digital camera controller and frame capture device in VHDL☆15Feb 11, 2013Updated 13 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆99Mar 19, 2026Updated 6 months ago
- A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…☆16Nov 5, 2017Updated 8 years ago
- [TPAMI] "Symbolic Visual Reinforcement Learning: A Scalable Framework with Object-Level Abstraction and Differentiable Expression Search"…☆18Jan 4, 2023Updated 3 years ago