FPGA-MAFIA / fpga_mafia
Designing a Multi-Agent Fabric Integration Architecture to run on de10-lite FPGA.
☆14Updated 2 weeks ago
Alternatives and similar repositories for fpga_mafia:
Users that are interested in fpga_mafia are comparing it to the libraries listed below
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated last year
- ☆11Updated last week
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 2 months ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆21Updated this week
- Alpha64 R10000 Two-Way Superscalar Processor☆12Updated 5 years ago
- DSP WishBone Compatible Cores☆13Updated 10 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆21Updated last week
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 7 years ago
- A collection of SPI related cores☆15Updated 3 months ago
- Ethernet MAC 10/100 Mbps☆25Updated 3 years ago
- Repository containing the DSP gateware cores☆12Updated 5 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- ☆33Updated 2 years ago
- double_fpu_verilog☆14Updated 10 years ago
- PCI bridge☆18Updated 10 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- A configurable general purpose graphics processing unit for☆11Updated 5 years ago
- ☆36Updated 2 years ago
- SystemC to Verilog Synthesizable Subset Translator☆9Updated last year
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆35Updated 4 years ago
- Open FPGA Modules☆23Updated 5 months ago
- An Open Source Link Protocol and Controller☆25Updated 3 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆16Updated 2 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆26Updated 4 years ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆16Updated last month
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Updated last year
- APB Logic☆15Updated 3 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year