GeekAlexis / superscalar-mips
A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines
☆10Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for superscalar-mips
- Alpha64 R10000 Two-Way Superscalar Processor☆11Updated 5 years ago
- A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.☆13Updated 2 years ago
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Updated last year
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆19Updated last month
- The RTL source for AnyCore RISC-V☆30Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆28Updated 3 weeks ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆27Updated 6 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆47Updated 2 years ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- ☆12Updated 4 months ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 5 years ago
- RISC-V soft-core PEs for TaPaSCo☆15Updated 5 months ago
- RISC-V Core Local Interrupt Controller (CLINT)☆24Updated last year
- Reconfigurable Binary Engine☆15Updated 3 years ago
- A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA wi…☆13Updated 4 years ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆18Updated 3 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆17Updated 7 months ago
- YSYX RISC-V Project NJU Study Group☆11Updated 2 years ago
- This is the fork of CVA6 intended for PULP development.☆16Updated last week
- corundum work on vu13p☆17Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆59Updated this week
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆16Updated last week
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆14Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆30Updated last year
- BlackParrot on Zynq☆25Updated this week
- cycle accurate Network-on-Chip Simulator☆25Updated last year
- RISC-V Matrix Specification☆15Updated 2 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago