GeekAlexis / superscalar-mipsLinks
A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines
☆11Updated 5 years ago
Alternatives and similar repositories for superscalar-mips
Users that are interested in superscalar-mips are comparing it to the libraries listed below
Sorting:
- Alpha64 R10000 Two-Way Superscalar Processor☆12Updated 6 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆32Updated last year
- RISC-V Core Local Interrupt Controller (CLINT)☆26Updated last year
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 7 months ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆12Updated this week
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆17Updated last month
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆13Updated 3 months ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- ☆23Updated 7 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Updated 2 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆27Updated 5 years ago
- The official NaplesPU hardware code repository☆16Updated 5 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- ☆11Updated 4 years ago
- Reconfigurable Binary Engine☆16Updated 4 years ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆20Updated 4 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆27Updated 2 weeks ago
- RISC-V soft-core PEs for TaPaSCo☆19Updated 11 months ago
- Platform Level Interrupt Controller☆40Updated last year
- CMake based hardware build system☆25Updated this week
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆33Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆60Updated 4 months ago
- ☆13Updated 3 weeks ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆19Updated 2 weeks ago
- Basic Verilog Ethernet core and C driver functions☆11Updated 3 months ago
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.☆16Updated 3 years ago
- This repo includes XiangShan's function units☆26Updated last week