Alpha64 R10000 Two-Way Superscalar Processor
☆12May 6, 2019Updated 7 years ago
Alternatives and similar repositories for Alpha64_R10000_Superscalar_Processor
Users that are interested in Alpha64_R10000_Superscalar_Processor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Jul 14, 2026Updated 2 weeks ago
- Some materials and sample source for RV32 OS projects.☆22May 31, 2022Updated 4 years ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆21Updated this week
- RISC-V SIMD Superscalar Dual-Issue Processor☆31Apr 24, 2025Updated last year
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆18Updated this week
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- ☆10Nov 2, 2023Updated 2 years ago
- ☆12May 29, 2020Updated 6 years ago
- HeliosXCore is a Superscalar Out-of-order RISC-V Processor Core.☆10Mar 8, 2024Updated 2 years ago
- Arduino Library for using ATSAMD processors with PDM microphones (w/I2S)☆16Mar 3, 2026Updated 4 months ago
- FPGA Labs for EECS 151/251A (Fall 2021)☆13Oct 20, 2021Updated 4 years ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆16Nov 23, 2018Updated 7 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines☆11Nov 28, 2019Updated 6 years ago
- Reconfigurable Binary Engine☆18Mar 23, 2021Updated 5 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- ☆12Jan 27, 2017Updated 9 years ago
- 4th RISC-V Workshop Tutorials☆13Jul 19, 2016Updated 10 years ago
- Open-source Neural Processing Unit (NPU) from China ❤☆52Jan 29, 2025Updated last year
- This is a brand new implement of GPGPU called Koala GPU which will be compatible with NV GPU micro architecture starting from fermi. It s…☆18May 31, 2026Updated last month
- The Verilog source code for DRUM approximate multiplier.☆32May 4, 2023Updated 3 years ago
- Pipelined 64-bit RISC-V core☆17Mar 7, 2024Updated 2 years ago
- Repo to help explain the different options users have for packaging.☆19Jun 8, 2022Updated 4 years ago
- Basic chisel difftest environment for RTL design (WIP☆21Mar 8, 2025Updated last year
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆17Sep 27, 2022Updated 3 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆18Jul 5, 2023Updated 3 years ago
- The RTL source for AnyCore RISC-V☆33Mar 18, 2022Updated 4 years ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆45May 5, 2023Updated 3 years ago
- ☆22Nov 3, 2025Updated 8 months ago
- Super scalar Processor design☆21Sep 7, 2014Updated 11 years ago
- SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations☆22Apr 12, 2026Updated 3 months ago
- ordspecsim: The Swarm architecture simulator☆25Feb 15, 2023Updated 3 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- BECE_Notes 📚 A comprehensive collection of organized study materials for Bachelor in Computer Engineering at Pokhara University. Contain…☆21Jun 21, 2026Updated last month
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- 给NEMU移植Linux Kernel!☆23Jun 1, 2025Updated last year
- 16-Point FFT is developed in order to accurately model that of the MATLAB function. . The module successfully tested using verilog testbe…☆19May 27, 2016Updated 10 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆23Nov 24, 2025Updated 8 months ago
- risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom☆18Sep 15, 2020Updated 5 years ago
- ☆22Sep 24, 2023Updated 2 years ago
- Radix-4 1024 point fft in verilog☆12Apr 29, 2020Updated 6 years ago
- ☆36May 21, 2026Updated 2 months ago