Alpha64 R10000 Two-Way Superscalar Processor
☆12May 6, 2019Updated 6 years ago
Alternatives and similar repositories for Alpha64_R10000_Superscalar_Processor
Users that are interested in Alpha64_R10000_Superscalar_Processor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Feb 23, 2026Updated last month
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Updated this week
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆20Apr 7, 2025Updated 11 months ago
- Some materials and sample source for RV32 OS projects.☆22May 31, 2022Updated 3 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆22Apr 25, 2025Updated 11 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- RISC-V SIMD Superscalar Dual-Issue Processor☆29Apr 24, 2025Updated 11 months ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆15Nov 23, 2018Updated 7 years ago
- ☆12May 29, 2020Updated 5 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆25Mar 24, 2026Updated last week
- HeliosXCore is a Superscalar Out-of-order RISC-V Processor Core.☆10Mar 8, 2024Updated 2 years ago
- ☆10Nov 2, 2023Updated 2 years ago
- FPGA Labs for EECS 151/251A (Fall 2021)☆11Oct 20, 2021Updated 4 years ago
- Arduino Library for using ATSAMD processors with PDM microphones (w/I2S)☆16Mar 3, 2026Updated 3 weeks ago
- 4th RISC-V Workshop Tutorials☆13Jul 19, 2016Updated 9 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Reconfigurable Binary Engine☆17Mar 23, 2021Updated 5 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- Pipelined 64-bit RISC-V core☆15Mar 7, 2024Updated 2 years ago
- A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines☆11Nov 28, 2019Updated 6 years ago
- ☆12Jan 27, 2017Updated 9 years ago
- This is the FreePDK45 V1.4 Process Development Kit for the 45 nm technology☆34Feb 22, 2021Updated 5 years ago
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆27Nov 1, 2025Updated 4 months ago
- Repo to help explain the different options users have for packaging.☆19Jun 8, 2022Updated 3 years ago
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 9 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- Basic chisel difftest environment for RTL design (WIP☆20Mar 8, 2025Updated last year
- A fork of Xiangshan for AI☆38Updated this week
- ☆18Jul 5, 2023Updated 2 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆15Mar 2, 2022Updated 4 years ago
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆16Sep 27, 2022Updated 3 years ago
- The Verilog source code for DRUM approximate multiplier.☆32May 4, 2023Updated 2 years ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43May 5, 2023Updated 2 years ago
- ☆22Nov 3, 2025Updated 4 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom☆15Sep 15, 2020Updated 5 years ago
- Recommended coding standard of Verilog and SystemVerilog.☆36Oct 21, 2021Updated 4 years ago
- Super scalar Processor design☆21Sep 7, 2014Updated 11 years ago
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆19Jan 9, 2026Updated 2 months ago
- ordspecsim: The Swarm architecture simulator☆24Feb 15, 2023Updated 3 years ago
- The RTL source for AnyCore RISC-V☆33Mar 18, 2022Updated 4 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago