eisl-nctu / aquila

Related projects ⓘ

Alternatives and complementary repositories for aquila

• kuopinghsu / srv32
  Simple 3-stage pipeline RISC-V processor
  ☆134Updated 6 months ago
• yutongshen / RISC-V_SoC
  ☆29Updated last year
• accomdemy / accomdemy_rv32i
  伴伴學 RISC-V RV32I Architecture CPU
  ☆24Updated 2 years ago
• eisl-nctu / falco
  A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.
  ☆13Updated 2 years ago
• bol-edu / caravel-soc
  ☆25Updated last year
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆124Updated 4 years ago
• mathis-s / SoomRV
  A simple superscalar out-of-order RISC-V microprocessor
  ☆178Updated this week
• chipsalliance / uvm-verilator
  ☆75Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆63Updated 7 months ago
• AlSaqr-platform / he-soc
  ☆33Updated this week
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆30Updated 2 months ago
• riscv / riscv-CMOs
  ☆81Updated 2 years ago
• ninolomata / bao-cva6-guide
  ☆9Updated last year
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆76Updated 2 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆67Updated 6 months ago
• AleksandarKostovic / SystemC-tutorial
  Brief SystemC getting started tutorial
  ☆83Updated 5 years ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆30Updated last year
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆62Updated 5 months ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆80Updated 3 years ago
• yutongshen / RISC-V-Simulator
  ☆26Updated last year
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆59Updated 3 years ago
• martinriis / RISC-V-Vector-Processor
  256-bit vector processor based on the RISC-V vector (V) extension
  ☆28Updated 3 years ago
• max2468tw / IC_Lab
  NCTU 2018 Spring Integrated Circuit Design Laboratory
  ☆24Updated 6 years ago
• albertfan1120 / NTU_CVSD_2021
  Computer-Aided VLSI System Design
  ☆16Updated last month
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆45Updated 5 years ago
• 4a1c0 / RV32i-Verilog
  Simple RiscV core for academic purpose.
  ☆22Updated 4 years ago
• oprecomp / DDR4_controller
  ☆48Updated 3 years ago
• kuopinghsu / biriscv
  biRISC-V - 32-bit dual issue RISC-V CPU Software Environment
  ☆10Updated 3 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆46Updated 2 years ago
• riscv / riscv-aclint
  ☆39Updated 2 years ago