eisl-nctu / aquilaLinks
Aquila: a 32-bit RISC-V processor for Xilinx FPGAs.
☆32Updated last year
Alternatives and similar repositories for aquila
Users that are interested in aquila are comparing it to the libraries listed below
Sorting:
- Simple 3-stage pipeline RISC-V processor☆140Updated last week
- ☆38Updated 2 years ago
- RISC-V Virtual Prototype☆172Updated 7 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated last month
- Ariane is a 6-stage RISC-V CPU☆141Updated 5 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆69Updated last year
- CVA6 SDK containing RISC-V tools and Buildroot☆72Updated last month
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 months ago
- ☆63Updated 4 years ago
- A simple superscalar out-of-order RISC-V microprocessor☆212Updated 5 months ago
- RISC-V Verification Interface☆100Updated 2 months ago
- A libgloss replacement for RISC-V that supports HTIF☆38Updated last year
- PCI Express controller model☆60Updated 2 years ago
- AIA IP compliant with the RISC-V AIA spec☆42Updated 6 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- RISC-V System on Chip Template☆159Updated this week
- This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop☆37Updated 4 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆56Updated last year
- ☆89Updated 3 years ago
- ☆49Updated 3 months ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆101Updated last week
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- ☆31Updated 4 months ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆59Updated 8 months ago
- Brief SystemC getting started tutorial☆92Updated 6 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 5 years ago