HPC-Lab-IITB / ClarinetLinks
A RISC-V processor written in BSV, based on the Flute core. Has support for integrating tightly-coupled accelerators, and for integrating custom functional units like posit arithmetic units.
☆23Updated 2 years ago
Alternatives and similar repositories for Clarinet
Users that are interested in Clarinet are comparing it to the libraries listed below
Sorting:
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- YosysHQ SVA AXI Properties☆41Updated 2 years ago
- LIS Network-on-Chip Implementation☆30Updated 8 years ago
- RISC-V soft-core PEs for TaPaSCo☆22Updated last year
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆38Updated 3 weeks ago
- SystemVerilog Functional Coverage for RISC-V ISA☆29Updated last month
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- Simple UVM environment for experimenting with Verilator.☆22Updated 2 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆65Updated 2 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆85Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆30Updated last week
- Implementation of post-process coverage, and batch waveform search☆15Updated 3 years ago
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 3 weeks ago
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆24Updated 6 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- RISC-V Nox core☆66Updated 3 months ago
- ☆47Updated 3 months ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆35Updated 2 years ago
- Platform Level Interrupt Controller☆41Updated last year