SJTU-ECTL / VECBEELinks
VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis
☆13Updated 3 years ago
Alternatives and similar repositories for VECBEE
Users that are interested in VECBEE are comparing it to the libraries listed below
Sorting:
- ☆28Updated 2 years ago
- An integrated CGRA design framework☆91Updated 7 months ago
- The open-sourced version of BOOM-Explorer☆43Updated 2 years ago
- A list of our chiplet simulaters☆43Updated 3 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆59Updated 4 months ago
- EDA wiki☆132Updated 6 months ago
- An Open-Source Tool for CGRA Accelerators☆74Updated last month
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆96Updated 3 months ago
- The first version of TritonPart☆29Updated last year
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆138Updated 4 months ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- Benchmarks for Approximate Circuit Synthesis☆17Updated 5 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆175Updated 2 months ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆29Updated 2 years ago
- ☆23Updated last year
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆85Updated 5 months ago
- ☆44Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆63Updated last month
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆63Updated 4 months ago
- ☆39Updated 2 years ago
- Library of approximate arithmetic circuits☆55Updated 3 years ago
- An Open-Source Tool for CGRA Accelerators☆25Updated last month
- reference block design for the ASAP7nm library in Cadence Innovus☆51Updated last year
- The template for VLSI project☆24Updated 2 years ago
- ☆50Updated 3 months ago
- ☆59Updated 6 months ago
- RTL generator for SpGEMM☆11Updated 4 years ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆19Updated 9 months ago
- A toolchain for rapid design space exploration of chiplet architectures☆61Updated 2 months ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆73Updated 2 years ago