polysome / evolvable_motherboard
Paul Layzell's Evolvable Motherboard
☆12Updated 9 years ago
Related projects ⓘ
Alternatives and complementary repositories for evolvable_motherboard
- Bachelor thesis Martijn Bakker -- Numerical mathematics on FPGAs using CλaSH☆28Updated 9 years ago
- An experimental System-on-Chip with a custom compiler toolchain.☆59Updated 4 years ago
- Verilog Tetris☆14Updated 9 years ago
- Synthesis-Aided Compiler for GreenArrays GA144☆51Updated 7 years ago
- A pipelined RISCV implementation in VHDL☆95Updated 5 years ago
- Stack CPU Work In Progress☆30Updated 10 months ago
- Automatically generates analog circuits using evolutionary algorithms☆255Updated 11 years ago
- ☆49Updated 9 years ago
- Source code form the Parallella Chronicles Blog☆15Updated 9 years ago
- FLVIz - Finite Automata Simulator written in QT/Graphviz☆36Updated 9 years ago
- Spacecraft Multicore Emulator Based on Leon 3 Sparc V8 architecture processor☆49Updated 5 years ago
- Experimental graphic editor for open FPGAs.☆49Updated 8 years ago
- An open source miniPCIe development board based on the Xilinx Spartan 6 LX150T☆141Updated 8 years ago
- Unsorted Playground for Machine Learning, Reinforcement Learning and other AI Experiments☆14Updated 2 years ago
- An AIMGP (Automatic Induction of Machine code by Genetic Programming) engine☆92Updated 5 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 3 years ago
- Yet Another Forth Core...☆70Updated 10 years ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 4 years ago
- An online Verilog IDE based on YosysJS.☆24Updated 8 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆37Updated 8 years ago
- Implementation of FizzBuzz on an FPGA☆17Updated 6 years ago
- An Actor-based framework for Lua☆38Updated 8 years ago
- ☆87Updated 5 years ago
- A Qt5 based free VLSI development tool☆30Updated 6 years ago
- A graph based REPL that saves to and loads from disk☆44Updated 9 years ago
- Exploration of alternative hardware description languages☆28Updated 6 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆54Updated 5 years ago
- a simple C-to-Verilog compiler☆47Updated 7 years ago
- A networked FPGA key-value store written in Clash☆27Updated 7 months ago
- Quickstart for Spatial language☆34Updated 4 years ago