polysome / evolvable_motherboardLinks
Paul Layzell's Evolvable Motherboard
☆13Updated 9 years ago
Alternatives and similar repositories for evolvable_motherboard
Users that are interested in evolvable_motherboard are comparing it to the libraries listed below
Sorting:
- Bachelor thesis Martijn Bakker -- Numerical mathematics on FPGAs using CλaSH☆28Updated 9 years ago
- Stack CPU Work In Progress☆30Updated last year
- Exploration of alternative hardware description languages☆28Updated 7 years ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 4 years ago
- RISC-V instruction set CPUs in HardCaml☆15Updated 8 years ago
- An experimental System-on-Chip with a custom compiler toolchain.☆60Updated 5 years ago
- Synthesis-Aided Compiler for GreenArrays GA144☆53Updated 8 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 3 years ago
- A Qt5 based free VLSI development tool☆30Updated 7 years ago
- RISC-V port to Parallella Board☆12Updated 8 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆56Updated 5 years ago
- Verilog Tetris☆13Updated 10 years ago
- Source code form the Parallella Chronicles Blog☆15Updated 9 years ago
- MRSIC32 ISA documentation and development☆90Updated last year
- ☆47Updated 9 years ago
- OpenFPGA☆34Updated 7 years ago
- Automatically generates analog circuits using evolutionary algorithms☆260Updated 12 years ago
- Spacecraft Multicore Emulator Based on Leon 3 Sparc V8 architecture processor☆50Updated 6 years ago
- A 6800 CPU written in nMigen☆49Updated 4 years ago
- Experimental graphic editor for open FPGAs.☆50Updated 9 years ago
- A compiler from Forth to Scratch☆22Updated 8 years ago
- an IDE that uses myHDL, yosys, and arachne-pnr to target the ICEStick☆12Updated 9 years ago
- An AIMGP (Automatic Induction of Machine code by Genetic Programming) engine☆92Updated 6 years ago
- ☆91Updated 5 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆40Updated 9 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- A reimplementation of a tiny stack CPU☆83Updated last year
- Yosys Plugins☆21Updated 5 years ago
- Discrete FPGA implementation☆59Updated 12 years ago
- Apollo CPU Core in Verilog. For learning and having fun with open FPGA☆44Updated 8 years ago