Alternatives and similar repositories for ApproxTrain

Users that are interested in ApproxTrain are comparing it to the libraries listed below

• dimdano / adapt
  Fast Emulation of Approximate DNN Accelerators in PyTorch
  ☆23Updated last year
• ehw-fit / tf-approximate
  Approximate layers - TensorFlow extension
  ☆27Updated 2 months ago
• fffasttime / AnyPackingNet
  ☆27Updated 2 months ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆54Updated this week
• ebby-s / MX-for-FPGA
  Implementation of Microscaling data formats in SystemVerilog.
  ☆20Updated 10 months ago
• CASR-HKU / DPACS
  ☆18Updated 2 years ago
• GATECH-EIC / DNN-Chip-Predictor
  [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…
  ☆25Updated 2 years ago
• gicLAB / SECDA
  ☆23Updated 2 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• isakedo / DNNsim
  ☆35Updated 4 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• abdelfattah-lab / BRAMAC
  ☆10Updated 6 months ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆39Updated 2 years ago
• awai54st / Logic-Shrinkage
  ☆23Updated 2 years ago
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated last year
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆39Updated 4 years ago
• maestro-project / gamma-timeloop
  ☆15Updated last year
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆79Updated 3 years ago
• maestro-project / confuciux
  ☆33Updated 3 years ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 4 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 4 months ago
• lukasc-ch / ExtendedBitPlaneCompression
  Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…
  ☆19Updated 5 years ago
• enyac-group / MaxEVA
  MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)
  ☆21Updated last year
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆36Updated 5 years ago
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆33Updated last year
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• awai54st / LUTNet
  ☆58Updated 5 years ago
• sharc-lab / FPGA_ECE8893
  ☆35Updated 3 months ago