maltanar / spmvaccsimLinks
A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.
☆14Updated 10 years ago
Alternatives and similar repositories for spmvaccsim
Users that are interested in spmvaccsim are comparing it to the libraries listed below
Sorting:
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆51Updated 8 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Updated 2 years ago
- Project repo for the POSH on-chip network generator☆49Updated 4 months ago
- DASS HLS Compiler☆29Updated last year
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 6 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Documentation for the entire CGRAFlow☆19Updated 3 years ago
- cycle accurate Network-on-Chip Simulator☆29Updated 2 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆42Updated 8 years ago
- Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level☆10Updated 8 years ago
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- Development of a Network on Chip Simulation using SystemC.☆34Updated 8 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- ☆27Updated 7 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆42Updated 2 months ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- ☆16Updated 7 years ago
- ☆27Updated 5 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- ☆87Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- Public release☆57Updated 5 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Updated 4 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 5 years ago
- Example code for Modern SystemC using Modern C++☆64Updated 2 years ago