maltanar / spmvaccsimLinks
A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.
☆14Updated 10 years ago
Alternatives and similar repositories for spmvaccsim
Users that are interested in spmvaccsim are comparing it to the libraries listed below
Sorting:
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 5 years ago
- Development of a Network on Chip Simulation using SystemC.☆32Updated 7 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- ☆27Updated 5 years ago
- ☆35Updated 4 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆13Updated 4 years ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆28Updated 4 years ago
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- Documentation for the entire CGRAFlow☆19Updated 3 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆11Updated 7 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- DASS HLS Compiler☆29Updated last year
- Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube☆12Updated 8 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆12Updated 9 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- ☆15Updated 2 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Updated 6 years ago
- ☆27Updated 7 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago