ehw-fit / tf-approximateLinks
Approximate layers - TensorFlow extension
☆27Updated 5 months ago
Alternatives and similar repositories for tf-approximate
Users that are interested in tf-approximate are comparing it to the libraries listed below
Sorting:
- ☆71Updated 5 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 4 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆57Updated 5 months ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆141Updated 5 years ago
- ☆72Updated 2 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- Simulator for BitFusion☆102Updated 5 years ago
- ☆35Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 7 months ago
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆26Updated last year
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆149Updated 4 months ago
- Eyeriss chip simulator☆36Updated 5 years ago
- ☆30Updated 6 months ago
- RTL implementation of Flex-DPE.☆112Updated 5 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆40Updated 2 years ago
- ☆35Updated 6 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆34Updated 2 years ago
- ☆60Updated 5 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Updated 4 years ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆84Updated last year
- Quantized Training for Convolutional Neural Networks using Xilinx Brevitas☆12Updated 3 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆20Updated 7 months ago
- Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators☆11Updated 6 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆72Updated last year
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆35Updated 3 years ago