☆12Apr 16, 2022Updated 3 years ago
Alternatives and similar repositories for tpu_v2
Users that are interested in tpu_v2 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆52Jan 14, 2021Updated 5 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- ☆12Feb 15, 2024Updated 2 years ago
- ☆14Mar 22, 2024Updated 2 years ago
- ☆25Apr 15, 2025Updated 11 months ago
- ☆46Sep 13, 2024Updated last year
- For CPU experiment☆14Feb 23, 2021Updated 5 years ago
- ☆15Aug 10, 2023Updated 2 years ago
- The ISA specification for the ZiCondOps extension.☆19Mar 21, 2024Updated 2 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- This repository integrates gem5 with Ramulator2, allowing gem5 to use Ramulator2 as its DRAM memory model. With the provided materials an…☆14Jun 7, 2025Updated 9 months ago
- Memory Compiler Tutorial☆14Oct 7, 2020Updated 5 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12May 14, 2019Updated 6 years ago
- Data Structure and Algorithm with C (2021 Spring)☆11Jan 22, 2026Updated 2 months ago
- double_fpu_verilog☆21Jul 17, 2014Updated 11 years ago
- Source code of the processing-in-memory simulator used in the GRIM-Filter paper published at BMC Genomics in 2018: "GRIM-Filter: Fast See…☆11Feb 5, 2018Updated 8 years ago
- A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…☆14Aug 23, 2024Updated last year
- ☆16May 9, 2022Updated 3 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆12Aug 26, 2021Updated 4 years ago
- ☆17Aug 27, 2019Updated 6 years ago
- Verilog implementation of Bresenham's line drawing algorithm.☆13Nov 22, 2015Updated 10 years ago
- Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project☆16Mar 9, 2020Updated 6 years ago
- A hardware accelerator for General Matrix Multiply, developed in SystemC using ESP.☆18May 26, 2021Updated 4 years ago
- ☆16Apr 6, 2022Updated 3 years ago
- A simulator integrates ChampSim and Ramulator.☆19Aug 18, 2025Updated 7 months ago
- C++ implementation for Sequence Pair fixed-outline chip floorplanner☆11Dec 27, 2022Updated 3 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆45Jul 28, 2017Updated 8 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆24May 8, 2020Updated 5 years ago
- ☆14Apr 24, 2023Updated 2 years ago
- Pytorch implementation of RAPQ, IJCAI 2022☆23Jul 19, 2023Updated 2 years ago
- Task scheduler with high availability.☆12Jul 26, 2021Updated 4 years ago
- Verilog implementation of Bubble Sorter and Odd Even Transposition Sorter.☆14Nov 22, 2015Updated 10 years ago
- Code for paper: Narrowing the Gap Between Serverless and its State with Storage Functions☆12Jul 10, 2020Updated 5 years ago
- This repository contains various patches to the OSCI systemc distribution to make it possible to compile the sources with latest GCC vers…☆23Jun 21, 2011Updated 14 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆23Oct 9, 2020Updated 5 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆17Aug 3, 2021Updated 4 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆24May 20, 2019Updated 6 years ago
- A scalable Eyeriss model in SystemC.☆34Jan 1, 2023Updated 3 years ago
- Test scripts for exploring PyTorch JIT and quantization capability☆11Mar 8, 2021Updated 5 years ago