Alternatives and similar repositories for tpu_v2

Users that are interested in tpu_v2 are comparing it to the libraries listed below

• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆64Updated last week
• neasotho / SystolicArray_FPGA
  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
  ☆13Updated 5 years ago
• kuladeepsaireddy / OpenNoc
  ☆37Updated 6 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆37Updated 4 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• AIC2021 / AIC2021_TPU_Template
  Template for project1 TPU
  ☆19Updated 4 years ago
• nietzhuang / Cycle-accurate-Eyeriss-model
  A scalable Eyeriss model in SystemC.
  ☆30Updated 2 years ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆28Updated 4 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆31Updated 4 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆59Updated last week
• gem5-X / TiC-SAT
  ☆18Updated 6 months ago
• hyoukjun / OpenSMART
  Public release
  ☆57Updated 6 years ago
• pulp-platform / fpu
  ☆56Updated 6 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆82Updated 4 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆77Updated 7 years ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆21Updated 2 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 7 months ago
• alibaba / vector-accelerating-unit
  vector accelerating unit
  ☆34Updated 4 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆81Updated 2 years ago
• hyoukjun / microswitch-noc
  ☆27Updated 6 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆78Updated 11 years ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆75Updated 3 years ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆37Updated 3 years ago
• pulp-platform / ITA
  ☆55Updated 6 months ago
• adervay1 / CIMulator
  a Computing In Memory emULATOR framework
  ☆14Updated last year
• ac-optimus / Convolution-using-systolic-arrays
  ☆71Updated 6 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆24Updated 4 years ago
• ahirsharan / 32-Bit-Floating-Point-Adder
  Verilog Implementation of 32-bit Floating Point Adder
  ☆43Updated 5 years ago
• vaughnbetz / COFFE
  ☆44Updated last year
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆34Updated last year