nitheeshkm / sigmoid_tanh_verilog

Related projects: ⓘ

• aniket0511 / Sigmoid-Function
  Hardware Implementation of Sigmoid Function using verilog HDL
  ☆13Updated 4 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆19Updated 3 weeks ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆29Updated 3 years ago
• dldldlfma / super_small_toy_tpu
  ☆12Updated 3 years ago
• pontazaricardo / Verilog_Calculator_Matrix_Multiplication
  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
  ☆47Updated 7 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆33Updated 5 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆121Updated 4 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆23Updated 2 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆62Updated last year
• zhan6841 / FPGA-Accelerator-for-AES-LeNet-VGG16
  FPGA/AES/LeNet/VGG16
  ☆86Updated 6 years ago
• thousrm / universal_NPU-CNN_accelerator
  hardware design of universal NPU(CNN accelerator) for various convolution neural network
  ☆55Updated this week
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆21Updated 3 years ago
• vincent08tw / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆17Updated 3 years ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆137Updated 6 months ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆45Updated 2 years ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆81Updated 3 years ago
• snagiri / CSE237D-PYNQ-SNN-Accelerator
  Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board
  ☆28Updated 5 years ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆21Updated 5 years ago
• LeoTheBestCoder / NTHU-ICLAB
  ☆35Updated this week
• vrishbhan / Matrix-Multiplication
  Design for 4 x 4 Matrix Multiplication using Verilog
  ☆26Updated 9 years ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆114Updated 3 months ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆10Updated 3 years ago
• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆45Updated 4 years ago
• AhmedAalaaa / 32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm
  This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…
  ☆33Updated last year
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆79Updated 3 years ago
• HWAC-DL / hwac_object_tracker
  FPGA accelerated TinyYOLO v2 object detection neural network
  ☆66Updated 6 years ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆18Updated 2 years ago
• ahirsharan / LSTM
  Single Long Short Term Memory (LSTM) cell : Verilog Implementation
  ☆28Updated 4 years ago
• chengquan / IC_FLOW
  ☆11Updated 8 months ago
• dldldlfma / eyeriss_v1
  ☆10Updated 5 years ago