Alternatives and similar repositories for sigmoid_tanh_verilog:

Users that are interested in sigmoid_tanh_verilog are comparing it to the libraries listed below

• aniket0511 / Sigmoid-Function
  Hardware Implementation of Sigmoid Function using verilog HDL
  ☆15Updated 5 years ago
• pontazaricardo / Verilog_Calculator_Matrix_Multiplication
  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
  ☆50Updated 7 years ago
• snagiri / CSE237D-PYNQ-SNN-Accelerator
  Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board
  ☆36Updated 5 years ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆27Updated 6 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆24Updated 3 years ago
• ahirsharan / LSTM
  Single Long Short Term Memory (LSTM) cell : Verilog Implementation
  ☆30Updated 4 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆16Updated 3 years ago
• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆47Updated 5 years ago
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆11Updated 4 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆30Updated 4 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆43Updated 2 years ago
• dldldlfma / super_small_toy_tpu
  ☆38Updated 4 years ago
• liyu-ao / PE-array-for-LeNet-accelerator-based-on-FPGA
  This is a 4*5 PE array for LeNet accelerator based on FPGA.
  ☆12Updated 2 years ago
• YucanLiu / VLSI_SNN
  A Spiking Neuron Network Project in Verilog Implementation
  ☆21Updated 7 years ago
• vrishbhan / Matrix-Multiplication
  Design for 4 x 4 Matrix Multiplication using Verilog
  ☆31Updated 9 years ago
• eda-lab / CNNAF-CNN-Accelerator
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆10Updated 3 years ago
• eldrickm / wakey_wakey
  EE 272B - VLSI Design Project
  ☆11Updated 3 years ago
• kuladeepsaireddy / OpenNoc
  ☆31Updated 5 years ago
• AnuragSChatterjee / Multilayer-Perception-MLP-Neural-Network-Implementation-In-FPGA
  A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…
  ☆14Updated last year
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆71Updated last year
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆32Updated last year
• hsiehong / tpu
  AIChip 2021 project, NCKU
  ☆18Updated 3 years ago
• neasotho / SystolicArray_FPGA
  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
  ☆14Updated 4 years ago
• Basantloay / Softmax_CNN
  This repository contains full code of Softmax Layer in Verilog
  ☆18Updated 4 years ago
• Mattjesc / Efficient-FPGA-CNN-Accelerator
  Efficient FPGA-Based Accelerator for Convolutional Neural Networks
  ☆11Updated 8 months ago
• yayouz / CNN-accelerator
  DMA controller for CNN accelerator
  ☆13Updated 7 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆63Updated 6 years ago
• CY0807 / ZYNQ_PL_CONV_ACC
  一个基于AXI接口的PL端卷积加速器，可由PS端调用
  ☆11Updated 2 years ago
• chengquan / IC_FLOW
  ☆16Updated last year
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆98Updated 4 years ago