nitheeshkm / sigmoid_tanh_verilogView external linksLinks
Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project
☆16Mar 9, 2020Updated 5 years ago
Alternatives and similar repositories for sigmoid_tanh_verilog
Users that are interested in sigmoid_tanh_verilog are comparing it to the libraries listed below
Sorting:
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- HDL implementation of a pipelined multilayer perceptron (neural network)☆17Sep 14, 2015Updated 10 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 9 years ago
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆18May 4, 2023Updated 2 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆17Feb 27, 2021Updated 4 years ago
- ES-203 Computer Organization & Architecture CNN on FPGA board☆17Feb 23, 2022Updated 3 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Mar 5, 2018Updated 7 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆27Jul 4, 2019Updated 6 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆22May 20, 2019Updated 6 years ago
- An automated HDC platform☆11Jan 29, 2026Updated 2 weeks ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆55Aug 12, 2017Updated 8 years ago
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- Systolic-array based Deep Learning Accelerator generator☆28Dec 11, 2020Updated 5 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆76Jul 31, 2018Updated 7 years ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 4 years ago
- Vector Symbolic Architecture library☆11Mar 27, 2023Updated 2 years ago
- sailVina用于Linux的反向对接脚本☆10Feb 14, 2021Updated 5 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- The Easy Way to Create VST Effects * Jesusonic Editor + JS 2 C++ Transpiler☆12Aug 7, 2015Updated 10 years ago
- Integrating Event-based Dynamic Vision Sensors with Sparse Hyperdimensional Computing☆12Jul 9, 2020Updated 5 years ago
- A library that you can use to build spiking neural network brains for your Arduino robots! Largely allows you to follow the paradigms of …☆10Nov 21, 2015Updated 10 years ago
- ☆10Apr 21, 2025Updated 9 months ago
- ☆10Dec 5, 2020Updated 5 years ago
- This repository contains the models and training scripts used in the papers: "Quantizing Spiking Neural Networks with Integers" (ICONS 20…☆13Oct 20, 2020Updated 5 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Jun 5, 2020Updated 5 years ago
- Neuromorphic ASIC with 96 neurons on Tiny Tapeout 7☆11May 25, 2024Updated last year
- Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"☆11Apr 20, 2023Updated 2 years ago
- Accompanying repository for the DAFx24 paper "Interpolation Filters for Antiderivative Antialiasing"☆12Sep 5, 2024Updated last year
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated 10 months ago
- A Verilog implementation of a hand-written digit recognition Neural Network☆10Nov 16, 2024Updated last year
- A DAS-based focused ultrasonic beam synthesis algorithm source code☆16Jun 2, 2025Updated 8 months ago
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆13Nov 4, 2022Updated 3 years ago
- Gowin USB3.0 Device Controller IP☆15Aug 20, 2024Updated last year
- ☆11Nov 24, 2020Updated 5 years ago
- Efficient single-pass hyperdimensional classifier. Mirror of https://gitlab.com/biaslab/onlinehd☆11Jan 31, 2021Updated 5 years ago
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆13Feb 16, 2024Updated last year
- Human activity recognition using hyperdimensional computing based on Kinect's skeleton data☆11Jun 5, 2017Updated 8 years ago
- ☆49Jan 14, 2021Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆65Aug 9, 2022Updated 3 years ago