minhhn2910 / QPyTorchLinks
Low Precision Arithmetic Simulation in PyTorch - extension for posit and beyond
☆14Updated 3 weeks ago
Alternatives and similar repositories for QPyTorch
Users that are interested in QPyTorch are comparing it to the libraries listed below
Sorting:
- Official implementation of "Searching for Winograd-aware Quantized Networks" (MLSys'20)☆27Updated last year
- ☆14Updated 5 years ago
- A Deep Learning Framework for the Posit Number System☆28Updated 10 months ago
- Approximate layers - TensorFlow extension☆27Updated 2 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 4 months ago
- ☆71Updated 5 years ago
- FPGA-based hardware acceleration for dropout-based Bayesian Neural Networks.☆24Updated last year
- Training with Block Minifloat number representation☆14Updated 4 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆33Updated last year
- ☆71Updated 2 years ago
- [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…☆16Updated 3 years ago
- ☆35Updated 4 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Updated 5 years ago
- ☆58Updated 5 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆31Updated 6 years ago
- Adaptive floating-point based numerical format for resilient deep learning☆14Updated 3 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- ☆20Updated 4 months ago
- ColTraIn HBFP Training Emulator☆16Updated 2 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Docker container with tools for the Timeloop/Accelergy tutorial☆22Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- Simulator for BitFusion☆100Updated 4 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆57Updated 3 years ago
- Python code to show how a systolic array works. Written for https://medium.com/@antonpaquin/whats-inside-a-tpu-c013eb51973e☆28Updated 7 years ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆139Updated 5 years ago
- Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators☆11Updated 6 years ago
- A Generic Distributed Auto-Tuning Infrastructure☆22Updated 3 years ago
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆23Updated last year
- Implementation for the paper "Latent Weights Do Not Exist: Rethinking Binarized Neural Network Optimization"☆74Updated 5 years ago