scale-lab / DRUMLinks
The Verilog source code for DRUM approximate multiplier.
☆31Updated 2 years ago
Alternatives and similar repositories for DRUM
Users that are interested in DRUM are comparing it to the libraries listed below
Sorting:
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Approximate arithmetic circuits for FPGAs☆12Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆65Updated 5 years ago
- ☆27Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated last week
- General Purpose AXI Direct Memory Access☆53Updated last year
- ☆34Updated 6 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 6 years ago
- ☆26Updated last year
- SRAM☆22Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆72Updated 4 years ago
- ☆65Updated 6 years ago
- SoC Based on ARM Cortex-M3☆32Updated last month
- Xilinx AXI VIP example of use☆41Updated 4 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆64Updated 8 years ago
- ☆43Updated 10 months ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- A verilog implementation for Network-on-Chip☆74Updated 7 years ago
- A RRAM addon for the NCSU FreePDK 45nm☆23Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 9 months ago
- Project repo for the POSH on-chip network generator☆48Updated 3 months ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆27Updated 3 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆41Updated 2 years ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Updated 7 years ago