scale-lab / DRUMLinks
The Verilog source code for DRUM approximate multiplier.
☆31Updated 2 years ago
Alternatives and similar repositories for DRUM
Users that are interested in DRUM are comparing it to the libraries listed below
Sorting:
- Approximate arithmetic circuits for FPGAs☆12Updated 5 years ago
- ☆27Updated 5 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- sram/rram/mram.. compiler☆37Updated last year
- ☆34Updated 6 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- General Purpose AXI Direct Memory Access☆57Updated last year
- eyeriss-chisel3☆41Updated 3 years ago
- SRAM☆22Updated 4 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Updated 7 years ago
- CNN accelerator☆27Updated 8 years ago
- ☆26Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 10 months ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆27Updated 3 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆66Updated 5 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆21Updated 5 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 6 years ago
- A verilog implementation for Network-on-Chip☆75Updated 7 years ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆41Updated 2 years ago
- Xilinx AXI VIP example of use☆41Updated 4 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆11Updated 9 months ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- ☆65Updated 6 years ago
- Project repo for the POSH on-chip network generator☆49Updated 4 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆73Updated 4 years ago
- A RRAM addon for the NCSU FreePDK 45nm☆23Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated 2 weeks ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆40Updated 2 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated this week
- APB Logic☆19Updated this week